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VX3030 User's Guide
4.3.1
P0 Connector
P0 Wafer Assignment
Wafer
ROW G
1
+12V
2
+12V
3
+5V
4
I2C1 CLK
5
GAP*
6
GA3*
7
GPIO5 (TCK)
8
GND
CASE
* signal active when low
CA.DT.A87-5e
ROW F
ROW E
+12V
+12V
+12V
+12V
+5V
+5V
I2C1 DAT
GND
GA4*
GND
GA2*
GND
GND
PCIe_CLK-
(TDO)
REF_CLK-
REF_CLK+
Table 19: VPX Connector P0 Wafer Assignment
ROW D
ROW C
NC
+3V3
NC
+3V3
NC
+5V
NC
GND
(-12V_AUX)
3V3_AUX
GND
NC
GND
(+12V_AUX)
PCIe_CLK+
GND
(TDI)
GND
AUX_CLK-
GND
Physical I/O
ROW B
ROW A
+3V3
+3V3
+3V3
+3V3
+5V
+5V
SYSRESET*
NVMRO
I2C0 CLK
I2C0 DAT
GA1*
GA0*
GPIO3
GPI04
(TMS)
(TRST)
AUX_CLK+
GND
Page 43
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