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VX3030 User's Guide
7.8.1
RP2 Connector
>
Legend for Table 37
COM1/2
Simplified Serial Lines
PCIe_CLK
Additionnal PCI express clock from PCH
PCIe_TX/RX
Additionnal PCI express x1 link from PCH
eDP-A/B
Digital ports A and B from PCH
RP2 Wafer Assignment
RPM
Row G
Wafer
1
COM2 TXD+
2
GND
PCIe CLK-
3
COM2 TXD
4
GND
5
COM2 RXD+
6
GND
7
COM2 RXD
8
GND
CASE
RP2 Signal Definition
Mnemonic
COMx
eDPx
PCIe1 TX/RX
PCIe1 CLK
Reserved
GND
CA.DT.A87-5e
Row F
Row E
GND
eDP-B 3-
PCIe CLK+
GND
PCIe TX-
Reserved
Reserved
GND
Reserved
Reserved
Reserved
GND
Reserved
Reserved
Reserved
Table 37: Rear I/O VPX Connector RP2 Wafer Assignment
Signal Definition
Serial Lines, EIA-232/EIA-485
embedded Display Port
Additional PCI-Express x1 link
Common Reference Clock Output for PCIe1
Reserved, do not connect
Ground
Table 38: Rear I/O VPX Connector RP2 Signal Definition
Row D
Row C
eDP-B 3+
GND
GND
eDP-B AUX-
PCIe TX+
GND
GND
Reserved
Reserved
GND
GND
Reserved
Reserved
GND
GND
Reserved
GND
VX3030-RTM Characteristics
Row B
Row A
eDP-B2-
eDP-B 2+
eDP-B AUX+
GND
PCIe RX-
PCIe RX+
Reserved
GND
Reserved
Reserved
Reserved
GND
Reserved
Reserved
Reserved
GND
Board
Wafer
P2 w09
P2 w10
P2 w11
P2 w12
P2 w13
P2 w14
P2 w15
P2 w16
Page 75
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