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Additional Board Features
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I2C bus 0 slave registers definition :
I2C_BOARD_STATUS @(Base_address) – When bit 3 of Register @(Base_address + 1) is set to 0
Bit#
Name
7
Power Status
6-5
Reset Source
4
Reset Status
3-0
Boot Status
I2C_BOARD_STATUS @(Base_address) – when bit 3 register @(Base_address + 1) is set to 1
Bit#
Name
7-0
Power Debug 1
Page 32
Description
Power Status
0 Power Stand By
1 Power ON
Last Reset Source
0x000 PWRGD_P3V3SB
0x001 Watchdog Expired
0x010 SYSRESET_INb
0x011 Maskable Reset
Reset Status Side A
0 No PWOK
1 PWOK
Boot Status
These bits are Read Only through I2C Slave
Interface and R/W through LPC Interface
Description
This register indicates State of Powers when a
power error occurs (falling of one of the
PWRGDG_XX signals).
This register is re-initialized only when Stand By
power is down.
Bit 7 : PWRGD_DDR
Bit 6 : PWRGD_GFXCORE
Bit 5 : PWRGD_P1V0
Bit 4 : PWRGD_P1V0_6U
Bit 3 : PWRGD_P1V05IBEX
Bit 2 : PWRGD_P1V05S
Bit 1 : PWRGD_P1V2_6U
Bit 0 : PWRGD_P1V5_6U
VX3030 User's Guide
Reset
Type
0
RO
0
RO
0
RO
0
RW
Reset
Type
0
RO
CA.DT.A87-5e
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