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Physical I/O
P0 Signal Definition
MNEMONIC
+12V
+12 Volts DC power (VS1 VPX supply). NC (+12V) pins are not connected (VS2 VPX
supply)
+5V
+5 Volts DC power (VS3 VPX supply)
+3V3
+3.3
Non-Volatile Memory Read Only. When asserted (logical 1), prevents any non-volatile
NVMRO
memory from being updated.
GAi
Geographical address pins
GAP
Geographical address parity
GND
Ground
GPIO
General Purpose I/Ox (handled by the CPLD A). JTAG signals are not used on P0.
I2C0
I2C Bus 0
I2C1
I2C Bus 1
REF_CLK+/-
The Reference Clock is a bussed differential pair. Output if the VX3030 is plugged in
the system controller slot, input otherwise.
It enables the entire system to synchronize to a common time reference if desired.
Counter/timer in the CPLD can use this clock
AUX_CLK+/-
1 PPS (one pulse per second) clock input. Can be programmed as an output on system
controller slot. Can be used to phase the CPLD timer/counter clocked by REF_CLK+/-.
PCIe_CLK+/-
Optional Common Reference PCI Express Clock input. Can also be programmed as an
output.
SYSRESET*
System Reset. Input and open collector output.
Page 44
Volts DC power (VS2 VPX supply)
Table 20: VPX Connector P0 Signal Definition
SIGNAL DEFINITION
VX3030 User's Guide
CA.DT.A87-5e
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