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Physical I/O
P2 Signal Definition
MNEMONIC
COMx
USBx PWR
USBx D+/-
SATAx RX+/-
SATAx TX+/-
eDPx
PCIe1 TX/RX
PCIe1 CLK
Reserved
GND
4.3.4
XDP
Standard XDP debug connector can be made available through a dedicated adapter board.
Page 48
Serial Lines, EIA-232/EIA-485
USB Power link x
Differential Data pair of USB link x
Serial ATA. Receive +/- link x
Serial ATA. Transmit +/- link x
embedded Display Port
Additional PCI-Express x1 link
Common Reference Clock Output for PCIe1
Reserved, do not connect
Ground
Table 24: VPX Connector P2 Signal Definition
SIGNAL DEFINITION
VX3030 User's Guide
CA.DT.A87-5e
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