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VX3030 User's Guide
4.3.2
P1 Connector
P1 Wafer Assignment
>
Legend for Table 21:
P1_VBAT
Battery Voltage
P1_SYS_CON*
System Controller
P1_REFCLK0-SE
Single ended Reference Clocks
PCIe0 LxRX | LxTX
x4 or 4x1 PCI-Express from CPU
Wafer
ROW G
1
GDISCRETE1
2
GND
3
VBAT
4
GND
5
SYS_CON*
6
GND
P1-REF_CLK_
7
SE
8
GND
9
USB2 PWR
10
GND
11
USB3 PWR
12
GND
13
GPIO1
14
GND
Maskable Reset*
15
or GPIO2
16
GND
CASE
* signal active when low
CA.DT.A87-5e
ROW F
ROW E
GND
PCIe0 L0-TX-
PCIe0 L1-TX-
PCIe0 L1-TX+
GND
PCIe0 L2-TX-
PCIe0 L3-TX-
PCIe0 L3-TX+
GND
NC
NC
NC
GND
NC
NC
NC
GND
SATA0 TX-
SATA3 TX-
SATA3 TX+
GND
NC
USB2 DA-
USB2 DA+
GND
ETH DB-
ETH DD
ETH DD+
GND
ETH1 TX-
ETH0 TX-
ETH0 TX+
Table 21: VPX Connector P1 Wafer Assignment
USB2/3
USB links 2 and 3 from PCH
SATA0/3
SATA links 0 and 3 from PCH
ETHx TX/RX
1000BASE-BX links 0 and 1 from Dual
GbE i82580
ETH DA/DB/DC/DD
1000BASE-T link from GbE i82577
ROW D
ROW C
PCIe0 L0-TX+
GND
GND
PCIe0 L1-RX-
PCIe0 L2-TX+
GND
GND
PCIe0 L3-RX-
NC
GND
GND
NC
NC
GND
GND
NC
SATA0 TX+
GND
GND
SATA3 RX-
NC
GND
GND
USB3 DA-
ETH DB+
GND
GND
ETH DC-
ETH1 TX+
GND
GND
ETH0 RX-
GND
Physical I/O
ROW B
ROW A
PCIe0 L0-RX-
PCIe0 L0-RX+
PCIe0 L1-RX+
GND
PCIe0 L2-RX-
PCIe0 L2-RX+
PCIe0 L3-RX+
GND
NC
NC
NC
GND
NC
NC
NC
GND
SATA0 RX-
SATA0 RX+
SATA3 RX+
GND
NC
NC
USB3 DA+
GND
ETH DA-
ETH DA+
ETH DC+
GND
ETH1 RX-
ETH1 RX+
ETH0 RX+
GND
Page 45
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