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Additional Board Features
There are 3 expiration modes:
a. Timer only mode
b. Reset mode
c. Interrupt mode
3.2
I2C Structure
Each CPU subsystem features three I2C busses.
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The first one is attached to the PCH Platform Hub Controller and controls the DDR3 SPD EEPROM, the low
power RTC, the CK505 clock generator and, for CPU only, the card Voltage monitoring device.
>
The remaining i2C busses are handled by the CPLD device according Figure 16 "I2C Diagram".
Page 30
Figure 16: I2C Diagram
VX3030 User's Guide
CA.DT.A87-5e
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