Cpld Features - Kontron VX3030 User Manual

VX3030 User's Guide
3.3

CPLD Features

The CPLD manages following features:
> Power-on/off control
> Reset control
> Local environmental control/monitoring
> LPC interface to processor
> I2C interfaces to I2C bus IPMB A/B (rear P0)
> LEDs control
> Serial lines multiplexer
> Serial VPD and user memories
> User and system GPIOs
> Internal registers that allow system management
VX3030 VPX I2C interfaces
VX3030 implements two I2C buses connected to P0 VPX connector (see P0 pin assignments):
I2C0 : CLK signal on pin P0/B5, DATA signal on pin P0/ A5
I2C1: CLK signal on pin P0/G4, DATA signal on pin P0/ F4
I2C bus 0 is a master/slave interface .
I2C bus 1 is a master only interface .
>
VPX I2C bus 0 / 1 master interfaces:
I2C bus 0/1 master interfaces software tools are described in Fedora relase note (SD.DT.F82)
>
VPX I2C bus 0 slave interface:
VX3030 board I2C bus 0 slave register base address depends on VPX slot ID (slot geographical address):
VPX Slot 1 (syscon): VX3030 slave I2C base address is 0x18 (I2C 7bits addressing)
VPX Slot 2: VX3030 slave I2C base address is 0x19 (I2C 7bits addressing)
VPX Slot 3: VX3030 slave I2C base address is 0x1A (I2C 7bits addressing)
And so on.....
CA.DT.A87-5e
Additional Board Features
Page 31