Gnss Control And Indication Interfaces - Quectel BG95 A-GL Series Hardware Design

4.8. GNSS Control and Indication Interfaces

On BG951A-GL module, the GNSS chip is independent of the baseband chip, therefore BG951A-GL
module supports the following additional GNSS control and indication pins compared with
BG950A-GL/BG953A-GL/BG955A-GL.
Table 32: Pin Definition of GNSS Control and Indication Interfaces
Pin Name Pin No.
GNSS_BOOT 75
GNSS_NRST 76
GNSS_EN 97
SFNIND_1PPS 98
GNSS_EN is used to enable the LDO that powers the GNSS chip internally. In addition, this LDO can be
enabled via the GPIO pins of the internal baseband chip. Pulling up GNSS_EN will power on the GNSS
chip. After the module is turned on, the external host can send AT+QGPS=1 to the GNSS chip via the
GNSS UART interface to enable the GNSS function, and then the GNSS chip will output the NEMA
sentences from the GNSS UART interface.
GNSS_BOOT is used to upgrade the firmware of the GNSS chip. First, pull up GNSS_BOOT, and then
pull up GNSS_EN to supply power for the GNSS chip. After the module is turned on, the GNSS chip will
enter the boot mode. At this time, you can use the QFlash tool to update the GNSS firmware. After the
update is completed, pull down GNSS_BOOT.
1PPS output via SFNIND_1PPS is disabled by default. You can enable it with AT+QGPSPPS=1.
BG95xA-GL_Hardware_Design
I/O Description
Force the GNSS chip of the
DI module into emergency
download mode
Reset the GNSS chip;
DI
Active high
DI Enable internal GNSS chip
DO One pulse per second
LPWA Module Series
Comment
1.8 V power domain.
If unused, keep these pins open.
Synchronized with the NMEA
sentences output time at the rising
edge. Pulse width: 100 ms.
If unused, keep it open.
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