Quectel BG95 A-GL Series Hardware Design page 28
Lpwa module
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Also See for BG95 A-GL Series:
- Hardware design (84 pages) ,
- Application note (57 pages) ,
- Manual (48 pages)
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USIM_CLK
46
USIM_GND
47
Main UART Interface
Pin
Pin Name
No.
MAIN_DTR
30
MAIN_RXD
34
MAIN_TXD
35
MAIN_CTS
36
MAIN_RTS
37
MAIN_DCD
38
MAIN_RI
39
Debug UART Interface
Pin
Pin Name
No.
DBG_RXD
22
DBG_TXD
23
Antenna Interfaces
Pin
Pin Name
No.
ANT_MAIN
60
BG95xA-GL_Hardware_Design
DO
(U)SIM card clock
Specified ground for
-
(U)SIM card
I/O
Description
Main UART data terminal
DI
ready
DI
Main UART receive
DO
Main UART transmit
DTE clear to send signal
DO
from DCE (Connect to
DTE's CTS)
DTE request to send
DI
signal from DCE
(Connect to DTE's RTS)
Main UART data carrier
DO
detect
Main UART ring
DO
indication
I/O
Description
DI
Debug UART receive
DO
Debug UART transmit
I/O
Description
AIO
Main antenna interface
LPWA Module Series
V
min = 1.26 V
IH
V
max = 2.0 V
IH
V
max = 0.36 V
OL
V
min = 1.44 V
OH
V
max = 0.36 V
OL
V
min = 1.44 V
OH
-
DC Characteristics
V
min = -0.2 V
IL
V
max = 0.54 V
IL
V
min = 1.26 V
IH
V
max = 2.0 V
IH
V
max = 0.36 V
OL
V
min = 1.44 V
OH
V
min = -0.2 V
IL
V
max = 0.54 V
IL
V
min = 1.26 V
IH
V
max = 2.0 V
IH
V
max = 0.36 V
OL
V
min = 1.44 V
OH
DC Characteristics
V
min = -0.2 V
IL
V
max = 0.54 V
IL
V
min = 1.26 V
IH
V
max = 2.0 V
IH
V
max = 0.36 V
OL
V
min = 1.44 V
OH
DC Characteristics
-
-
Comment
1.8 V power
domain.
If unused, keep
these pins open.
Comment
1.8 V power
domain.
If unused, keep
these pins open.
Comment
50 Ω impedance
27 / 102
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