Quectel BG95 A-GL Series Hardware Design page 9

Table Index
Table 1: Special Mark
Table 2: Brief Introduction of the Module
Table 3: Wireless Network Types
Table 4: Key Features
Table 5: I/O Parameters Definition
Table 6: Pin Definition – Pins with Same Functions on BG95xA-GL
Table 7: Pin Definition – Pins with Different Functions on BG95xA-GL
Table 8: Operating Mode Overview
Table 9: Power Supply Pin Definition of BG950A-GL/BG951A-GL/BG953A-GL
Table 10: Power Supply Pin Definition of BG955A-GL
Table 11: PWRKEY Pin Definition
Table 12: RESET_N Pin Definition
Table 13: Pin Definition of PON_TRIG
Table 14: (U)SIM Interface Pin Definition
Table 15: USB Interface Pin Definition
Table 16: Main UART Interface Pin Definition
Table 17: Debug UART Interface Pin Definition
Table 18: BG950A-GL & BG953A-GL & BG955A-GL CLI UART Interface Pin Definition
Table 19: BG951A-GL CLI UART Interface Pin Definition
Table 20: BG951A-GL GNSS UART Interface Pin Definition
Table 21: Pin Definition of ADC Interfaces
Table 22: Characteristics of ADC Interfaces
Table 23: PSM_IND Pin Definition
Table 24: Pin Definition of NET_STATUS
Table 25: Working State of Network Connection Status Indication
Table 26: STATUS Pin Definition
Table 27: MAIN_RI Pin Definition
Table 28: MAIN_RI Default Behaviors
Table 29: GRFC Interface Pin Definitions
Table 30: GRFC Interface Truth Table
Table 31: GPIO Interface Pin Definitions
Table 32: Pin Definition of GNSS Control and Indication Interfaces
Table 33: Pin Definition of Cellular Network Interface
Table 34: Operating Frequency
Table 35: RF Output Power
Table 36: Conducted RF Receiving Sensitivity of BG950A-GL/BG951A-GL
Table 37: Conducted RF Receiving Sensitivity of BG955A-GL
Table 38: Pin Definition of GNSS Antenna Interface
Table 39: BG950A-GL & BG953A-GL & BG955A-GL GNSS Frequency
Table 40: BG951A-GL GNSS Frequency
Table 41: BG950A-GL & BG953A-GL GNSS Performance
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