Quectel BG95 A-GL Series Hardware Design page 49

NOTE
1. VDD_1V8 is provided by an external LDO.
2. If the host's voltage domain is not 3.3 V, the value of the voltage divider resistors should be tested
according to your actual application.
3. Inside the module, PON_TRIG is connected in series with a diode and connected in parallel with a
10 kΩ pull-down resistor to the ground. Therefore, the actual voltage divider value needs to be
measured.
The following is a brief description of PON_TRIG use.
PON_TRIG is pulled down by default. Before the module is turned on, PON_TRIG must be pulled up.

Otherwise, the main UART interface will be inaccessible.
When the module is powered on, pull down PON_TRIG within 200 ms after sending AT+QPOWED or

driving PWRKEY low, after which the module will execute the power-down procedure. For more
details, see Chapter 3.9.
After sending AT+QPSMS to enable PSM, driving PON_TRIG low will set the module to PSM. Drive

PON_TRIG high and keep it high, the module will wake up from PSM. In this case, PON_TRIG must
remain high, otherwise the module will re-enter PSM.
Pull down PON_TRIG and keep it low in e-l-DRX, PSM, sleep or power off mode. In other cases, pull

up PON_TRIG and keep it high to make sure the main UART is accessible. For details about
PON_TRIG use in e-l-DRX and sleep modes, see Chapter 3.4 and Chapter 3.5 respectively.
BG95xA-GL_Hardware_Design
Figure 22: PON_TRIG Reference Circuit 2
LPWA Module Series
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