Control And Indication Interfaces - Quectel RM502Q-GL Hardware Design

Table 11: Pin Definition of PCM Interface*
Pin No. Pin Name
20 PCM_CLK
22 PCM_DIN
24 PCM_DOUT
28 PCM_SYNC
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer
to document [2] for details about AT+QDAI command.
NOTE
"*" means under development.

3.10. Control and Indication Interfaces

The following table shows the pin definition of control and indication pins.
Table 12: Pin Definition of Control and Indication Interfaces
Pin No. Pin Name
8 W_DISABLE1#*
10 WWAN_LED#*
23 WAKE_ON_WAN#*
25 DPR*
26 W_DISABLE2#*
38 SDX2AP_STATUS
RM502Q-GL_Hardware_Design
I/O Description
IO PCM data bit clock
DI PCM data input
DO PCM data output
IO PCM data frame sync
I/O Description
DI Airplane mode control. Active LOW.
It is an open drain and active low signal.
OD
Indicate RF status of the module.
Wake up the host.
OD
It is an open drain and active low signal.
Dynamic power reduction. High level by
DI
default.
DI GNSS disable control. Active LOW.
DO Status indication to AP
5G Module Series
RM502Q-GL Hardware Design
Comment
1.8 V power domain
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
1.8 V power domain
1.8 V power domain
1.8 V power domain
Comment
1.8/3.3 V
1.8 V
1.8/3.3 V
1.8 V power
domain
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