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Quectel BG772A-GL Hardware Design

Quectel BG772A-GL Hardware Design

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BG772A-GL
Hardware Design
LPWA Module Series
Version: 1.0.0
Date: 2021-01-28
Status: Preliminary
www.quectel.com

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  • Page 1 BG772A-GL Hardware Design LPWA Module Series Version: 1.0.0 Date: 2021-01-28 Status: Preliminary www.quectel.com...
  • Page 2 To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable.
  • Page 3 BG772A-GL Hardware Design Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design.

  • Page 4: Safety Information

    Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 5: About The Document

    LPWA Module Series BG772A-GL Hardware Design About the Document Revision History Version Date Author Description Besson RONG/ 2021-01-28 Creation of the document Ben JIANG Besson RONG/ 1.0.0 2021-01-28 Preliminary Ben JIANG BG772A-GL_Hardware_Design 4 / 75...

  • Page 6: Table Of Contents

    LPWA Module Series BG772A-GL Hardware Design Contents Safety Information..............................3 About the Document..............................4 Contents..................................5 Table Index................................... 7 Figure Index................................. 9 Introduction............................... 10 1.1. Special Mark............................13 Product Concept...............................14 2.1. General Description..........................14 2.2. Features............................15 2.3. Functional Diagram..........................17 2.4. Evaluation Board............................ 18 Application Interfaces.............................19...
  • Page 7 LPWA Module Series BG772A-GL Hardware Design 3.16. ADC Interfaces*............................47 3.17. GPIO Interfaces*............................ 48 3.18. GRFC Interfaces*........................... 49 GNSS Receiver*..............................50 4.1. General Description..........................50 4.2. GNSS Performance..........................50 4.3. Layout Guidelines...........................51 Antenna Interfaces............................52 5.1. Main Antenna Interface......................... 52 5.1.1.
  • Page 8 Table 33: Power Supply Ratings..........................60 Table 34: Operating and Storage Temperatures....................61 Table 35: BG772A-GL Current Consumption (Power Supply: 3.3 V, Room Temperature)......62 Table 36: GNSS Current Consumption (Power Supply: 3.3 V, Room Temperature)........64 Table 37: 1.8 V I/O Requirements..........................
  • Page 9 LPWA Module Series BG772A-GL Hardware Design Table 42: Recommended Thermal Profile Parameters..................74 Table 43: BG772A-GL Packaging Specifications....................75 Table 44: Related Documents..........................76 Table 45: Terms and Abbreviations........................76 BG772A-GL_Hardware_Design 8 / 75...
  • Page 10 LPWA Module Series BG772A-GL Hardware Design Figure Index Figure 1: Functional Diagram..........................17 Figure 2: Pin Assignment (Top View)........................20 Figure 3: Sleep Mode Application via UART......................30 Figure 4: Star Structure of the Power Supply....................... 31 Figure 5: Turn on the Module by Using Driving Circuit..................

  • Page 11: Introduction

    The document, coupled with application notes and user guides, makes it easy to design and to set up mobile applications with BG772A-GL. Hereby, [Quectel Wireless Solutions Co., Ltd.] declares that the radio equipment type [BG772A-GL] is in compliance with Directive 2014/53/EU.
  • Page 12 LPWA Module Series BG772A-GL Hardware Design must not exceed: Operating Band LTE BAND 2 7.300 7.30 LTE BAND 4 4.300 4.30 LTE BAND 5 8.841 5.40 LTE BAND 12 8.098 4.91 LTE BAND 13 8.514 5.23 LTE BAND 25 7.300 7.30...
  • Page 13 LPWA Module Series BG772A-GL Hardware Design unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

  • Page 14: Special Mark

    LPWA Module Series BG772A-GL Hardware Design doit être clairement visible en tout temps lorsqu'il est installédans le produit hôte; sinon, le produit hôte doit porter une étiquette indiquant le numéro de certification d'Innovation, Sciences et Développement économique Canada pour le module, précédé du mot «Contient» ou d'un libellé semblable exprimant la même signification, comme suit:...

  • Page 15: Product Concept

    Product Concept 2.1. General Description BG772A-GL is an embedded IoT (LTE Cat M1, LTE Cat NB1/Cat NB2*) wireless communication module. It provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also provides optional GNSS* and voice* functionality to meet customers’...

  • Page 16: Key Features

    LPWA Module Series BG772A-GL Hardware Design With a compact profile of 14.9 mm × 12.9 mm × 1.9 mm, BG772A-GL can meet almost all requirements for M2M applications such as smart metering, tracking system, security, wireless POS, etc. It is especially suitable for size and weight sensitive applications such as smart watch and other wearable devices.
  • Page 17 LPWA Module Series BG772A-GL Hardware Design Debug UART: Used for firmware upgrade, software debugging and log output  115200 bps baud rate by default  The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) ...

  • Page 18: Functional Diagram

    LPWA Module Series BG772A-GL Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of BG772A-GL and illustrates the major functional parts. Power management  Baseband  Radio frequency  Peripheral interfaces  Figure 1: Functional Diagram NOTE PCM and I2C interfaces are for VoLTE* only.

  • Page 19: Evaluation Board

    BG772A-GL Hardware Design 2.4. Evaluation Board To facilitate application development with BG772A-GL conveniently, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cables, USB data cables, earphone, antennas and other peripherals to control or test the module. For more details, see document [2].

  • Page 20: Application Interfaces

    LPWA Module Series BG772A-GL Hardware Design Application Interfaces BG772A-GL is equipped with 94 LGA pads that can be connected to customers’ cellular application platforms. The subsequent chapters will provide detailed description of interfaces listed below: Power supply  PON_TRIG interface* ...

  • Page 21: Pin Assignment

    LPWA Module Series BG772A-GL Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG772A-GL. Figure 2: Pin Assignment (Top View) BG772A-GL_Hardware_Design 20 / 75...

  • Page 22: Pin Description

    Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. PCM and I2C interfaces are for VoLTE* only. 3.2. Pin Description The following tables show the pin definition of BG772A-GL. Table 4: Definition of I/O Parameters Type Description...
  • Page 23 LPWA Module Series BG772A-GL Hardware Design Table 5: Pin Description Power Supply Pin Name Pin No. Description Comment Characteristics Power supply for Vmax = 4.35 V VBAT_BB the module’s Vmin = 2.2 V Refer to NOTE 1 baseband part Vnom = 3.3 V Power supply for Vmax = 4.2 V...
  • Page 24 LPWA Module Series BG772A-GL Hardware Design Compliant with USB USB differential USB_DP 2.0 standard data (+) specification. Require USB differential differential impedance USB_DM data (-) of 90 Ω. Power supply for USBPHY_3P3 Vnom = 3.3 V USB PHY circuit External LDO...
  • Page 25 LPWA Module Series BG772A-GL Hardware Design Debug UART Interface Pin Name Pin No. Description Comment Characteristics Debug UART DBG_RXD DI/PU 1.8 V receive Debug UART DBG_TXD DO/PU 1.8 V transmit If this pin is unused, keep it open. Debug UART clear...
  • Page 26 LPWA Module Series BG772A-GL Hardware Design External pull-up resistor is required. I2C serial data (for I2C_SDA 1.8 V only. external codec) If this pin is unused, keep it open. Antenna Interfaces Pin Name Pin No. Description Comment Characteristics Main antenna ANT_MAIN 50 Ω...
  • Page 27 LPWA Module Series BG772A-GL Hardware Design Other Interface Pins Pin Name Pin No. Description Comment Characteristics Pulled up by default. When it is at low voltage level, the Airplane mode W_DISABLE#* DI/PU 1.8 V module can enter control airplane mode.

  • Page 28: Operating Modes

    LPWA Module Series BG772A-GL Hardware Design 3.3. Operating Modes The table below briefly summarizes the various operating modes of BG772A-GL. Table 6: Overview of Operating Modes Mode Details The module is connected to network. Its current consumption varies Connected with the network setting and data transfer rate.

  • Page 29: Power Saving

    The execution of AT+CFUN command will not affect GNSS function. 3.4.2. Power Saving Mode (PSM)* BG772A-GL module minimizes its power consumption through entering PSM. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections.

  • Page 30: Extended Idle Mode Drx (E-I-Drx)

    NOTE See document [4] for details about AT+CEDRXS. 3.4.4. Sleep Mode BG772A-GL can reduce its current consumption to a lower value during the sleep mode. The following sub-chapters describe the power saving procedure of BG772A-GL. 3.4.4.1.UART Application If the host communicates with the module via UART interface, the following preconditions can let the module enter sleep mode.

  • Page 31: Power Supply

    The following figure shows the connection between the module and the host. Figure 3: Sleep Mode Application via UART When BG772A-GL has a URC to report, MAIN_RI signal will wake up the host. See Chapter 3.14 for  details about MAIN_RI behavior.

  • Page 32: Decrease Voltage Drop

    The power supply VBAT_BB range of BG772A-GL is from 2.2 V to 4.35 V, the power supply VBAT_RF range of BG772A-GL is from 3.1 V to 4.2 V. When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V.

  • Page 33: Turn On And Off Scenarios

    LPWA Module Series BG772A-GL Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Pin Definition of PWRKEY The following table shows the pin definition of PWRKEY. Table 8: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment max = 0.3 V...
  • Page 34 LPWA Module Series BG772A-GL Hardware Design Figure 6: Turn on the Module by Using Keystroke The power-up scenario is illustrated in the following figure. Figure 7: Power-up Timing BG772A-GL_Hardware_Design 33 / 75...

  • Page 35: Turn Off Module

    LPWA Module Series BG772A-GL Hardware Design NOTE Ensure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms. 3.6.3. Turn off Module Either of the following methods can be used to turn off the module normally: Turn off the module through PWRKEY.

  • Page 36: Reset The Module

    LPWA Module Series BG772A-GL Hardware Design 3.7. Reset the Module RESET_N is used to reset the module. The module can be reset by driving RESET_N low for minimum assertion time 100 ms. Table 9: Pin Definition of RESET_N Pin Name Pin No.

  • Page 37: Pon_Trig

    Ensure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG* BG772A-GL provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects high level for minimum assertion time 100 μs, the module will wake up from PSM.

  • Page 38: U)Sim Interface

    Figure 12: Reference Circuit of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG772A-GL supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 11: Pin Definition of (U)SIM Interface Pin Name...
  • Page 39 LPWA Module Series BG772A-GL Hardware Design BG772A-GL supports (U)SIM card hot-plug via USIM_DET, and both high- and low- level detections are supported. The function is disabled by default, and see AT+QSIMDET in document [4] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.

  • Page 40: Usb Interface

    (U)SIM card connector. 3.10. USB Interface* BG772A-GL contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports operation at full-speed (12 Mbps) mode only. The USB interface is under development, it is not recommended to use at present.
  • Page 41 LPWA Module Series BG772A-GL Hardware Design The following figures illustrate reference designs of USB PHY and USB interface. Figure 15: Reference Design of USB PHY Figure 16: Reference Design of USB Interface To ensure the integrity of USB data trace signal, components R3 and R4 should be placed close to the module, and also these resistors should be placed close to each other.

  • Page 42: Uart Interfaces

    LPWA Module Series BG772A-GL Hardware Design attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection devices as close to the USB connector as possible.  NOTES 1. The USB interface is under development, it is not recommended to use at present.
  • Page 43 LPWA Module Series BG772A-GL Hardware Design MAIN_RI* DO/PU Main UART ring indication NOTE AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command can be used to set the hardware flow control (the function is disabled by default). See document [4] for more details about these AT commands.
  • Page 44 LPWA Module Series BG772A-GL Hardware Design Figure 17: Main UART Reference Design (Translator Chip) Visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. For the design of circuits in dotted lines, refer to that of circuits in solid lines, but pay attention to the direction of connection.

  • Page 45: Pcm And I2C Interfaces

    BG772A-GL Hardware Design 3.12. PCM and I2C Interfaces* BG772A-GL provides one Pulse Code Modulation (PCM) digital interface and one I2C interface for VoLTE only. The following table shows the pin definition of the two interfaces which can be applied on audio codec design.

  • Page 46: Network Status Indication

    BG772A-GL Hardware Design 3.13. Network Status Indication* BG772A-GL provides one network status indication pin: NET_STATUS. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NET_STATUS in different network activity status.

  • Page 47: Status

    LPWA Module Series BG772A-GL Hardware Design 3.14. STATUS The STATUS pin is used to indicate the operation status of BG772A-GL. It outputs high level when the module powers on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name Pin No.

  • Page 48: Adc Interfaces

    LPWA Module Series BG772A-GL Hardware Design The default MAIN_RI behaviors can be configured flexibly by AT+QCFG="urc/ri/ring"* command. For more details about AT+QCFG, see document [3]. NOTE A URC can be outputted from UART port, through configuration via AT+QURCCFG. 3.16. ADC Interfaces* The module provides two analog-to-digital converter (ADC) interfaces.

  • Page 49: Gpio Interfaces

    LPWA Module Series BG772A-GL Hardware Design NOTES ADC input voltage must not exceed 1.8 V. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the divider’s resistor accuracy should be no less than 1 %.

  • Page 50: Grfc Interfaces

    LPWA Module Series BG772A-GL Hardware Design 3.18. GRFC Interfaces* The module provides two generic RF control interfaces for the control of external antenna tuners. Table 24: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 Generic RF controller 1.8 V power domain.

  • Page 51: Gnss Receiver

    UART interface by default. By default, BG772A-GL GNSS engine is switched off. It has to be switched on via AT command. The module does not support concurrent operation of WWAN and GNSS. For more details about GNSS engine technology and configurations, see document [1].

  • Page 52: Layout Guidelines

    LPWA Module Series BG772A-GL Hardware Design @ open sky XTRA enabled Accuracy Autonomous CEP-50 1.41 (GNSS) @ open sky NOTES Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously).

  • Page 53: Antenna Interfaces

    LPWA Module Series BG772A-GL Hardware Design Antenna Interfaces BG772A-GL includes a main antenna interface and a GNSS antenna interface. The impedance of antenna port is 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below.

  • Page 54: Reference Design Of Main Antenna Interface

    LPWA Module Series BG772A-GL Hardware Design LTE-FDD B13 777–787 746–756 LTE-FDD B17 704–716 734–746 LTE-FDD B18 815–830 860–875 LTE-FDD B19 830–845 875–890 LTE-FDD B20 832–862 791–821 LTE-FDD B25 1850–1915 1930–1995 LTE-FDD B26 814–849 859–894 LTE-FDD B27 807–824 852–869 LTE-FDD B28 703–748...

  • Page 55: Gnss Antenna Interface

    LPWA Module Series BG772A-GL Hardware Design 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. 5.2.1. Pin Definition Table 29: Pin Definition of GNSS Antenna Interface Pin Name Pin No. Description...

  • Page 56: Antenna Installation

    LPWA Module Series BG772A-GL Hardware Design NOTE The module of BG772A-GL is designed with a passive antenna. 5.3. Antenna Installation 5.3.1. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of RF traces is usually determined by the trace width (W), the materials’...
  • Page 57 LPWA Module Series BG772A-GL Hardware Design Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout...

  • Page 58: Antenna Requirements

    LPWA Module Series BG772A-GL Hardware Design For more details about RF layout, see document [5]. 5.3.2. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 31: Antenna Requirements Antenna Type Requirements Frequency range: 1559–1609 MHz Polarization: RHCP or linear VSWR: <...

  • Page 59: Recommended Rf Connector For Antenna Installation

    LPWA Module Series BG772A-GL Hardware Design 5.3.3. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connectors provided by HIROSE. Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.
  • Page 60 LPWA Module Series BG772A-GL Hardware Design The following figure describes the space factor of mated connector. Figure 30: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com. BG772A-GL_Hardware_Design 59 / 75...

  • Page 61: Electrical, Reliability And Radio Characteristics

    LPWA Module Series BG772A-GL Hardware Design Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 32: Absolute Maximum Ratings Parameter Min.

  • Page 62: Operating And Storage Temperatures

    LPWA Module Series BG772A-GL Hardware Design the minimum and maximum values. Power supply for USB USBPHY_3P3 PHY circuit USB_VBUS USB connection detect 1.19 NOTE When the module starts up normally, in order to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V.

  • Page 63: Current Consumption

    LPWA Module Series BG772A-GL Hardware Design 6.4. Current Consumption The following table shows current consumption of BG772A-GL. Room Temperature Table 35: BG772A-GL Current Consumption (Power Supply: 3.3 V, Description Conditions Avg. Max. Unit Leakage Power-off @ USB/UART disconnected μA PSM @ USB/UART disconnected μA...
  • Page 64 LPWA Module Series BG772A-GL Hardware Design LTE-FDD B12 @ dBm LTE-FDD B13 @ dBm LTE-FDD B18 @ dBm LTE-FDD B19 @ dBm LTE-FDD B20 @ dBm LTE-FDD B25 @ dBm LTE-FDD B26 @ dBm LTE-FDD B27 @ dBm LTE-FDD B28A @ dBm...

  • Page 65: Digital I/O Characteristic

    LPWA Module Series BG772A-GL Hardware Design LTE-FDD B66 @ dBm Room Temperature Table 36: GNSS Current Consumption (Power Supply: 3.3 V, Description Conditions Typ. Unit Cold start @ Instrument Searching Hot start @ Instrument (AT+CFUN=0) Lost state @ Instrument Instrument environment @ Passive antenna...

  • Page 66: Rf Output Power

    LTE-FDD B17 is supported by Cat NB2 only. LTE-FDD B26 and B27 are supported by Cat M1 only. 6.7. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG772A-GL. Table 40: BG772A-GL Conducted RF Receiving Sensitivity Receiving Sensitivity (dBm)
  • Page 67 LPWA Module Series BG772A-GL Hardware Design LTE-FDD B8 TBD/-99.8 TBD/-107.5 LTE-FDD B12 TBD/-99.3 TBD/-107.5 LTE-FDD B13 TBD/-99.3 TBD/-107.5 LTE-FDD B17 Not Supported TBD/-107.5 LTE-FDD B18 TBD/-102.3 TBD/-107.5 LTE-FDD B19 TBD/-102.3 TBD/-107.5 LTE-FDD B20 TBD/-99.8 TBD/-107.5 LTE-FDD B25 TBD/-100.3 TBD/-107.5 LTE-FDD B26 TBD/-100.3...

  • Page 68: Electrostatic Discharge

    The following table shows the electrostatic discharge characteristics of BG772A-GL module. Table 41: Electrostatic Discharge Characteristics (Temperature: 25 ºC, Relative Humidity: 45 %)

  • Page 69: Mechanical Dimensions

    LPWA Module Series BG772A-GL Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1. Top and Side Dimensions Pin 1...
  • Page 70 LPWA Module Series BG772A-GL Hardware Design Pin 1 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. BG772A-GL_Hardware_Design 69 / 75...

  • Page 71: Recommended Footprint

    LPWA Module Series BG772A-GL Hardware Design 7.2. Recommended Footprint Figure 33: Recommended Footprint (Top View) NOTES For easy maintenance of the module, keep a distance of about 3 mm between the module and other components on the motherboard. All reserved pins must be kept open.

  • Page 72: Top And Bottom Views

    Figure 34: Top and Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, refer to the module received from Quectel. BG772A-GL_Hardware_Design 71 / 75...

  • Page 73: Storage, Manufacturing And Packaging

    LPWA Module Series BG772A-GL Hardware Design Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %.

  • Page 74: Manufacturing And Soldering

    LPWA Module Series BG772A-GL Hardware Design NOTES This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed.

  • Page 75: Packaging

    PCB or shielding cover, and prevent the coating material from flowing into the module. 8.3. Packaging BG772A-GL is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application.
  • Page 76 LPWA Module Series BG772A-GL Hardware Design Figure 36: Tape Dimensions Figure 37: Reel Dimensions Table 43: BG772A-GL Packaging Specifications MOQ for MP Minimum Package: 500 Minimum Package x 4 = 2000 Size: 370 mm × 350 mm × 56 mm Size: 380 mm ×...

  • Page 77: Appendix A References

    Quectel_BG772A-GL_GNSS_Application_Note BG772A-GL GNSS Application Note Quectel_UMTS&LTE_EVB_User_Guide UMTS&LTE EVB User Guide AT+QCFG Commands Manual for Quectel_BG772A-GL_QCFG_AT_Commands_Manual BG772A-GL Module AT Commands Manual of BG772A-GL Quectel_BG772A-GL_AT_Commands_Manual Module Quectel_RF_Layout_Application_Note RF Layout Application Note Quectel_Module_Secondary_SMT_Application_Note Module Secondary SMT User Guide Table 45: Terms and Abbreviations...
  • Page 78 LPWA Module Series BG772A-GL Hardware Design e-I-DRX Extended Idle Mode Discontinuous Reception Evolved Packet Core Electrostatic Discharge Frequency Division Duplex Home Subscriber Server Inter-Integrated Circuit Low Noise Amplifier Low Pass Filter Long Term Evolution Mobile Originated Mobile Terminated Password Authentication Protocol...
  • Page 79 LPWA Module Series BG772A-GL Hardware Design Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VSWR...

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