Quectel BG95 A-GL Series Hardware Design page 30

AP_READY 19
PON_TRIG 96
GRFC Interface
Pin
Pin Name
No.
GRFC1 83
GRFC2 84
External GNSS LNA Interface
Pin
Pin Name
No.
GNSS_LNA_
51
EN
VDD_RF 99
RESERVED Pins
Pin Name Pin No.
RESERVED 4–7, 11–14, 16, 40, 41, 56, 57, 63, 77, 78, 92, 93
GND Pins
Pin Name Pin No.
3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67–74, 79–82, 89–91,
GND
100–102
The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to
5
keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected.
BG95xA-GL_Hardware_Design
Application processor
DI
sleep state detect
Used for main UART
function control and for
DI entering/exiting e-l-DRX,
PSM, sleep or power off
modes
I/O Description
DO Generic RF controller
DO Generic RF controller
5
I/O Description
External GNSS LNA
DO
enable
Can be used for external
PO
GNSS LNA power supply
LPWA Module Series
V min = -0.2 V
IL
V max = 0.54 V
IL
V min = 1.26 V
IH
V max = 2.0 V
IH
V min = -0.2 V
IL
V max = 0.3 V
IL
V min = 1 V
IH
V max = 1.98 V
IH
DC Characteristics
V max = 0.36 V
OL
V min = 1.44 V
OH
V max = 2.0 V
OH
DC Characteristics
V max = 0.38 V
OL
V min = 1.36 V
OH
Vnom = 1.9 V
I max = 50 mA
O
1.8 V power
domain.
If unused, keep this
pin open.
1.8 V power
domain.
Pulled down by
default.
Comment
1.8 V power
domain.
If unused, keep
these pins open.
Comment
1.8 V power
domain.
If unused, keep this
pin open.
If unused, keep this
pin open.
Comment
Keep these pins
open.
Comment
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