Main_Ri; Grfc Interfaces - Quectel BG95 A-GL Series Hardware Design

4.5.4. MAIN_RI

AT+QCFG= "risignaltype","physical" can be used to configure MAIN_RI behavior. No matter on which
port a URC is presented, the URC will trigger the behavior of MAIN_RI.
Table 27: MAIN_RI Pin Definition
Pin Name Pin No.
MAIN_RI 39
The default MAIN_RI behaviors can be configured flexibly with AT+QCFG="urc/ri/ring". See
document [2] for details. The default behavior of the MAIN_RI is shown below.
Table 28: MAIN_RI Default Behaviors
State Response
Idle MAIN_RI remains at a high level.
URC MAIN_RI outputs a 120 ms low pulse when a new URC is returned.
NOTE
A URC can be outputted from the main UART interface (default), the debug UART or EMUX ports by
configuring URC indication option with AT+QURCCFG. See document [3] for details about
AT+QURCCFG.

4.6. GRFC Interfaces

The module has two generic RF control interfaces for the control of external antenna tuners.
Table 29: GRFC Interface Pin Definitions
Pin Name Pin No.
GRFC1 83
GRFC2 84
BG95xA-GL_Hardware_Design
I/O Description
DO Main UART ring indication
I/O Description
DO Generic RF controller
DO Generic RF controller
LPWA Module Series
Comment
1.8 V power domain.
If unused, keep this pin open.
Comment
1.8 V power domain.
If unused, keep them open.
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