Quectel BG95 A-GL Series Hardware Design page 47

The reset timing is illustrated in the following figure.
NOTE
1. Ensure that there is no large capacitance on RESET_N pin.
2. Because PWRKEY and RESET traces are sensitive signal traces, it's necessary to surround the
traces with ground on that layer and with ground planes above and below, and keep their traces away
from each other, so as to reduce interference.
BG95xA-GL_Hardware_Design
Figure 19: Reference Circuit of RESET_N with a Button
Figure 20: Reset Timing
LPWA Module Series
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