Memory System Timing; Table C-8 Memory Addressing For 2-Way Interleaving; Table C-9 Memory Addressing For 4-Way Interleaving - Sun Microsystems Ultra 80 Service Manual

TABLE C-8
particular size being installed in banks 0 and 1.
with 4-way interleaving with 16 DIMMs of a particular size being installed in banks
0, 1, 2, and 3.
TABLE C-8
DIMM Size/Quantity
64-Mbyte/4
64-Mbyte/4
256-Mbyte/4
256-Mbyte/4
TABLE C-9
DIMM Size/Quantity
64-Mbyte/4
64-Mbyte/4
64-Mbyte/4
64-Mbyte/4
256-Mbyte/4
256-Mbyte/4
256-Mbyte/4
256-Mbyte/4
C.1.5.3

Memory System Timing

The QSC ASIC generates the memory addresses and control signals to the memory
system. The UPA clock is the clock source for the QSC ASIC and operates as fast as
120 MHz.
C.1.6 Graphics and Imaging
The system takes advantage of UPA features to provide high-performance graphics.
High-performance graphics can include a vertical, single buffer UPA graphics card, a
vertical, double buffer plus Z (DBZ) UPA graphics card, or an Elite3D UPA graphics
card. The UPA graphics card consists of the frame buffer controller (FBC) ASIC, the
lists memory addressing with 2-way interleaving with eight DIMMs of a
Memory Addressing for 2-Way Interleaving
DIMM Bank
0
1
0
1
Memory Addressing for 4-Way Interleaving
DIMM Bank
0
1
2
3
0
1
2
3
lists memory addressing
TABLE C-9
Addressing
0 x 0000.0000 to 0 x 1fff.ff80
0 x 0000.0040 to 0 x 1fff.ffc0
0 x 0000.0000 to 0 x 3fff.ffff)
0 x 0000.0040 to 0 x 7fff.ffco
Addressing
0 x 0000.0000 to 0 x 3fff.ff00
0 x 0000.0040 to 0 x 3fff.ff40
0 x 0000.0080 to 0 x 3fff.ff80
0 x 0000.00c0 to 0 x 8fff.ffco
0 x 0000.0000 to 0 x ffff.ff00
0 x 0000.0040 to 0 x ffff.ff40
0 x 0000.0080 to 0 x ffff.ff80
0 x 0000.00c0 to 0 x ffff.ffc0
Appendix -15