Sun Microsystems Ultra 80 Service Manual page 57

diag-level Variable Set to max (2-Way CPU) (Continued)
CODE EXAMPLE 3-2
2> <00> IMMU TSB Reg Test
2> <00> IMMU Tag Access Reg Test
2> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB RAM Access Test
1> <00> CPU Addr Align Trap Test
1> <00> DMMU Access Priv Page Test
1> <00> DMMU Write Protected Page Test
1> <1f> Init Psycho
1> <1f> Psycho Cntl and UPA Reg Test
1> <1f> Psycho DMA Scoreboard Reg Test
1> <1f> Psycho Perf Cntl Reg Test
1> <1f> PIO Decoder and BCT Test
1> <1f> PCI Byte Enable Test
1> <1f> Counter/Timer Limit Regs Test
1> <1f> Timer Reload Test
1> <1f> Timer Periodic Test
1> <1f> Mondo Int Map (short) Reg Test
1> <1f> Mondo Int Set/Clr Reg Test
1> <1f> Psycho IOMMU Regs Test
1> <1f> Psycho IOMMU RAM NTA Test
1> <1f> Psycho IOMMU CAM NTA Test
1> <1f> Psycho IOMMU RAM Address Test
1> <1f> Psycho IOMMU CAM Address Test
1> <1f> IOMMU TLB Compare Test
1> <1f> IOMMU TLB Flush Test
1> <1f> Stream Buff A Control Reg Test
1> <1f> Psycho ScacheA Page Tag Addr Test
1> <1f> Psycho ScacheA Line Tag Addr Test
1> <1f> Psycho ScacheA RAM Addr Test
1> <1f> Psycho ScacheA Page Tag NTA Test
1> <1f> Psycho ScacheA Line Tag NTA Test
1> <1f> Psycho ScacheA Error Status NTA Test
1> <1f> Psycho ScacheA RAM NTA Test
1> <1f> Stream Buff B Control Reg Test
1> <1f> Psycho ScacheB Page Tag Addr Test
1> <1f> Psycho ScacheB Line Tag Addr Test
1> <1f> Psycho ScacheB RAM Addr Test
1> <1f> Psycho ScacheB Page Tag NTA Test
1> <1f> Psycho ScacheB Line Tag NTA Test
1> <1f> Psycho ScacheB Error Status NTA Test
1> <1f> Psycho ScacheB RAM NTA Test
1> <1f> PBMA PCI Config Space Regs Test
1> <1f> PBMA Control/Status Reg Test
1> <1f> PBMA Diag Reg Test
1> <1f> PBMB PCI Config Space Regs Test
1> <1f> PBMB Control/Status Reg Test
Chapter -19