Sun Microsystems Ultra 80 Service Manual page 69

diag-level Variable Set to min (4-Way CPU) (Continued)
CODE EXAMPLE 3-4
3> <00> IU ASI Access Test
1> <00> IU ASI Access Test
2> <00> IU ASI Access Test
3> <00> FPU ASI Access Test
1> <00> FPU ASI Access Test
2> <00> FPU ASI Access Test
3> <00> Dcache RAM Test
2> <00> Dcache RAM Test
1> <00> Dcache RAM Test
3> <00> Dcache Tag Test
2> <00> Dcache Tag Test
1> <00> Dcache Tag Test
3> <00> Icache RAM Test
2> <00> Icache RAM Test
1> <00> Icache RAM Test
3> <00> Icache Tag Test
2> <00> Icache Tag Test
1> <00> Icache Tag Test
3> <00> Icache Next Test
2> <00> Icache Next Test
1> <00> Icache Next Test
3> <00> Icache Predecode Test
2> <00> Icache Predecode Test
1> <00> Icache Predecode Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
0> <1f> PIO Write Error, Target Abort Test
0> <1f> Timer Increment Test
0> <1f> Init Psycho
0> <1f> Consistent DMA UE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
3> <00> V9 Instruction Test
1> <00> V9 Instruction Test
2> <00> V9 Instruction Test
3> <00> CPU Tick and Tick Compare Reg Test
1> <00> CPU Tick and Tick Compare Reg Test
2> <00> CPU Tick and Tick Compare Reg Test
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00>Test 0: prefetch_mr
0> <00>Test 1: prefetch to non-cacheable page
Chapter -31