Sun Microsystems Ultra 80 Service Manual page 54

diag-level Variable Set to max (2-Way CPU)
CODE EXAMPLE 3-2
Executing Power On SelfTest
1>
1>@(#) Sun U80(UltraSPARC-II 4-way) UPA/PCI POST 1.2.5 04/05/1999
09:42 AM
1>INFO: Processor 1 is master. CPU 450 MHz. 4304KB Ecache.
1>
1> <00> Init System BSS
1> <00> NVRAM Battery Detect Test
1> <00> NVRAM Scratch Addr Test
1> <00> DMMU TLB Tag Access Test
1> <00> DMMU TLB RAM Access Test
1> <00> IMMU TLB Tag Access Test
1> <00> IMMU TLB RAM Access Test
1> <00> Probe Ecache
1> <00> Ecache RAM Addr Test
1> <00> Ecache Tag Addr Test
1> <00> Ecache Tag Test
1> <00> Invalidate Ecache Tags
1>INFO: Processor 0 is missing or disabled.
1>INFO: Processor 2 - UltraSPARC-II.
1>INFO: Processor 3 is missing or disabled.
1> <00> Init SC Regs
1> <00> SC Address Reg Test
1> <00> SC Reg Index Test
1> <00> SC Regs Test
1> <00> SC Dtag RAM Addr Test
1> <00> SC Cache Size Init
1> <00> SC Dtag RAM Data Test
1> <00> SC Dtag Init
1> <00> Probe Memory
1>INFO: 0MB Bank 0
1>INFO: 1024MB Bank 1
1>INFO: 512MB Bank 2
1>INFO: 1024MB Bank 3
1> <00> Malloc Post Memory
1> <00> Init Post Memory
1> <00> Post Memory Addr Test
1> <00> Map PROM/STACK/NVRAM in DMMU
1> <00> Memory Stack Test
2> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB RAM Access Test
2> <00> IMMU TLB Tag Access Test
2> <00> IMMU TLB RAM Access Test
2> <00> Probe Ecache
-16 Sun Ultra 80 Service Manual • March 2000