Sun Microsystems Ultra 80 Service Manual page 59

diag-level Variable Set to max (2-Way CPU) (Continued)
CODE EXAMPLE 3-2
1> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Lpbk Test
1> <1f> Stream DMA Rd, IOMMU Miss, Scache(prev rd) Hit Ebus Test
1> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev rd) Lpbk Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit Ebus Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev rd) Lpbk Test
1> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit(prev wr) Ebus Test
1> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev wr) Lpbk Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit(prev wr) Ebus Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev wr) Lpbk Test
1> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Ebus Test
1> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Lpbk Test
1> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Ebus Test
1> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Ebus Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Ebus Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Ebus Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Ebus Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Lpbk Test
1> <1f> Pass-Thru DMA Rd, Ebus device Test
1> <1f> Pass-Thru DMA Rd, Loopback Mode Test
1> <1f> Pass-Thru DMA Wr, Ebus device Test
1> <1f> Pass-Thru DMA Wr, Loopback Mode Test
1> <1f> Consist DMA Rd, IOMMU LRU Lock Ebus Test
1> <1f> Consist DMA Rd, IOMMU LRU Lock Lpbk Test
1> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Rd, IOMMU miss, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Rd, IOMMU Miss, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Ebus Test
1> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Lpbk Test
1> <1f> Consist DMA Wr, IOMMU LRU Locked Ebus Test
1> <1f> Consist DMA Wr, IOMMU LRU Lock Lpbk Test
1> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Ebus Test
1> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Lpbk Test
1> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Ebus Test
1> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Lpbk Test
Chapter -21