Sun Microsystems Ultra 80 Service Manual page 47

diag-level Variable Set to max (4-Way CPU) (Continued)
CODE EXAMPLE 3-1
3> <00> Update Slave Stack/Frame Ptrs
1> <00> Map PROM/STACK/NVRAM in DMMU
2> <00> Update Slave Stack/Frame Ptrs
0> <00> DMMU Hit/Miss Test
1> <00> Update Slave Stack/Frame Ptrs
0> <00> IMMU Hit/Miss Test
0> <00> DMMU Little Endian Test
0> <00> IU ASI Access Test
0> <00> FPU ASI Access Test
3> <00> DMMU Hit/Miss Test
1> <00> DMMU Hit/Miss Test
2> <00> DMMU Hit/Miss Test
3> <00> IMMU Hit/Miss Test
1> <00> IMMU Hit/Miss Test
2> <00> IMMU Hit/Miss Test
3> <00> DMMU Little Endian Test
1> <00> DMMU Little Endian Test
2> <00> DMMU Little Endian Test
3> <00> IU ASI Access Test
1> <00> IU ASI Access Test
2> <00> IU ASI Access Test
3> <00> FPU ASI Access Test
1> <00> FPU ASI Access Test
2> <00> FPU ASI Access Test
3> <00> Dcache RAM Test
2> <00> Dcache RAM Test
1> <00> Dcache RAM Test
3> <00> Dcache Tag Test
2> <00> Dcache Tag Test
1> <00> Dcache Tag Test
3> <00> Icache RAM Test
2> <00> Icache RAM Test
1> <00> Icache RAM Test
3> <00> Icache Tag Test
2> <00> Icache Tag Test
1> <00> Icache Tag Test
3> <00> Icache Next Test
2> <00> Icache Next Test
1> <00> Icache Next Test
3> <00> Icache Predecode Test
2> <00> Icache Predecode Test
1> <00> Icache Predecode Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
Chapter -9