Sun Microsystems Ultra 80 Service Manual page 46

diag-level Variable Set to max (4-Way CPU) (Continued)
CODE EXAMPLE 3-1
0> <00> SC Address Reg Test
0> <00> SC Reg Index Test
0> <00> SC Regs Test
0> <00> SC Dtag RAM Addr Test
0> <00> SC Cache Size Init
0> <00> SC Dtag RAM Data Test
0> <00> SC Dtag Init
0> <00> Probe Memory
0>INFO: 0MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> Malloc Post Memory
0> <00> Init Post Memory
0> <00> Post Memory Addr Test
0> <00> Map PROM/STACK/NVRAM in DMMU
0> <00> Memory Stack Test
3> <00> DMMU TLB Tag Access Test
1> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB Tag Access Test
3> <00> DMMU TLB RAM Access Test
2> <00> DMMU TLB RAM Access Test
1> <00> DMMU TLB RAM Access Test
3> <00> IMMU TLB Tag Access Test
2> <00> IMMU TLB Tag Access Test
1> <00> IMMU TLB Tag Access Test
3> <00> IMMU TLB RAM Access Test
2> <00> IMMU TLB RAM Access Test
1> <00> IMMU TLB RAM Access Test
3> <00> Probe Ecache
2> <00> Probe Ecache
3> <00> Ecache RAM Addr Test
2> <00> Ecache RAM Addr Test
1> <00> Probe Ecache
3> <00> Ecache Tag Addr Test
2> <00> Ecache Tag Addr Test
1> <00> Ecache RAM Addr Test
3> <00> Ecache Tag Test
2> <00> Ecache Tag Test
1> <00> Ecache Tag Addr Test
1> <00> Ecache Tag Test
3> <00> Invalidate Ecache Tags
2> <00> Invalidate Ecache Tags
1> <00> Invalidate Ecache Tags
3> <00> Map PROM/STACK/NVRAM in DMMU
2> <00> Map PROM/STACK/NVRAM in DMMU
-8 Sun Ultra 80 Service Manual • March 2000