Sun Microsystems Ultra 80 Service Manual page 74

diag-level Variable Set to min (Single CPU) (Continued)
CODE EXAMPLE 3-6
2> <00> Post Memory Addr Test
2> <00> Map PROM/STACK/NVRAM in DMMU
2> <00>Memory Stack Test
2> <00> DMMU Hit/Miss Test
2> <00> IMMU Hit/Miss Test
2> <00> DMMU Little Endian Test
2> <00> IU ASI Access Test
2> <00> FPU ASI Access Test
2> <1f> Init Psycho
2> <1f> PIO Read Error, Master Abort Test
2> <1f> PIO Read Error, Target Abort Test
2> <1f> PIO Write Error, Master Abort Test
2> <1f> PIO Write Error, Target Abort Test
2> <1f> Timer Increment Test
2> <1f> Init Psycho
2> <1f> Consistent DMA UE ECC Rd Err Lpbk Test
2> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
2> <00> V9 Instruction Test
2> <00> CPU Tick and Tick Compare Reg Test
2> <00> CPU Soft Trap Test
2> <00> CPU Softint Reg and Int Test
2> <00> UltraSPARC-2 Prefetch Instructions Test
2> <00>Test 0: prefetch_mr
2> <00>Test 1: prefetch to non-cacheable page
2> <00>Test 2: prefetch to page with dmmu misss
2> <00>Test 3: prefetch miss does not check alignment
2> <00>Test 4: prefetcha with asi 0x4c is noped
2> <00>Test 5: prefetcha with asi 0x54 is noped
2> <00>Test 6: prefetcha with asi 0x6e is noped
2> <00>Test 7: prefetcha with asi 0x76 is noped
2> <00>Test 8: prefetch with fcn 5
2> <00>Test 9: prefetch with fcn 2
2> <00>Test 10: prefetch with fcn 12
2> <00>Test 11: prefetch with fcn 16 is noped
2> <00>Test 12: prefetch with fcn 29 is noped
2> <00>Test 13: prefetcha with asi 0x15 is noped
2> <00>Test 14: prefetch with fcn 3
2> <00>Test 15: prefetcha14 with fcn 2
2> <00>Test 16: prefetcha80_mr
2> <00>Test 17: prefetcha81_1r
2> <00>Test 18: prefetcha10_mw
2> <00>Test 19: prefetcha80_17 is noped
2> <00>Test 20: prefetcha10_6: illegal instruction trap
2> <00>Test 21: prefetcha11_1w
2> <00>Test 22: prefetcha81_31
2> <00>Test 23: prefetcha11_15: illegal instruction trap
-36 Sun Ultra 80 Service Manual • March 2000