Table C-1 Upa Interconnect; Table C-2 Upa Port Identification Assignments - Sun Microsystems Ultra 80 Service Manual

C.1.2 UPA
The UltraSPARC port architecture (UPA) provides a packet-based interconnect
between the UPA clients: CPU modules, U2P ASIC, and UPA graphics cards.
Electrical interconnection is provided through four address buses and four data
buses.
UPA Interconnect
TABLE C-1
Bus Name Bus Designation
UPA address bus 0 UPA_AD0
UPA address bus 1 UPA_AD1
UPA address bus 2 UPA_AD2
UPA address bus 3 UPA_AD3
UPA data bus 0 UPA_DATA0
UPA data bus 1 UPA_DATA1
UPA data bus 2 UPA_D_DAT
UPA data bus 3 UPA_E_DAT
The following table lists UPA port identification assignments. The following figure
illustrates how the UPA address and data buses are connected between the UPA and
the UPA clients.
TABLE C-2
UPA Slot Number
CPU module slot 0
CPU module slot 1
-4 Sun Ultra 80 Service Manual • March 2000
Bus Type
Address
Address
Address
Address
Data
Data
Data
Data
UPA Port Identification Assignments
Function
Connects the QSC ASIC to the CPU modules and
the U2P ASIC.
Connects the QSC ASIC to the CPU modules and
the U2P ASIC.
Connects the QSC ASIC to the U2P ASIC.
Connects the QSC ASIC to the UPA graphics.
A bidirectional 144-bit data bus (128 bits of data
and 16 bits of ECC) that connects CPU modules 0
and 1 to the XB9++ ASIC.
A bidirectional 144-bit data bus (128 bits of data
and 16 bits of ECC) that connects CPU modules 2
and 3 to the XB9++ ASIC.
A 72-bit data bus (64 bits of data and eight bits of
ECC) that connects the XB9++ ASIC and the U2P
ASIC.
A 64-bit data bus that connects the U2P ASIC
and the UPA graphics.
UPA Port ID <4:0>
0x0
0x1