Sun Microsystems Ultra 80 Service Manual page 55

diag-level Variable Set to max (2-Way CPU) (Continued)
CODE EXAMPLE 3-2
2> <00> Ecache RAM Addr Test
2> <00> Ecache Tag Addr Test
2> <00> Ecache Tag Test
2> <00> Invalidate Ecache Tags
2> <00> Map PROM/STACK/NVRAM in DMMU
2> <00> Update Slave Stack/Frame Ptrs
1> <00> DMMU Hit/Miss Test
1> <00> IMMU Hit/Miss Test
1> <00> DMMU Little Endian Test
1> <00> IU ASI Access Test
1> <00> FPU ASI Access Test
2> <00> DMMU Hit/Miss Test
2> <00> IMMU Hit/Miss Test
2> <00> DMMU Little Endian Test
2> <00> IU ASI Access Test
2> <00> FPU ASI Access Test
2> <00> Dcache RAM Test
2> <00> Dcache Tag Test
2> <00> Icache RAM Test
2> <00> Icache Tag Test
2> <00> Icache Next Test
2> <00> Icache Predecode Test
1> <1f> Init Psycho
1> <1f> PIO Read Error, Master Abort Test
1> <1f> PIO Read Error, Target Abort Test
1> <1f> PIO Write Error, Master Abort Test
1> <1f> PIO Write Error, Target Abort Test
1> <1f> Timer Increment Test
1> <1f> Init Psycho
1> <1f> Consistent DMA UE ECC Rd Err Lpbk Test
1> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
1> <00> V9 Instruction Test
1> <00> CPU Tick and Tick Compare Reg Test
1> <00> CPU Soft Trap Test
1> <00> CPU Softint Reg and Int Test
2> <00> V9 Instruction Test
2> <00> CPU Tick and Tick Compare Reg Test
1> <00> Copy Post to Memory
1> <00> Ecache Thrash Test
1> <00> ECC Mem Addr Clear
1> <00> Memory Addr w/ Ecache Test
1>INFO: No memory in Bank 0
1>INFO: 1024MB Bank 1
1>INFO: 512MB Bank 2
1>INFO: 1024MB Bank 3
1> <00> Block Memory Addr Test
Chapter -17