Sun Microsystems Ultra 80 Service Manual page 292

PROM
RAMDAC
RC
RISC
SB
SCSI
SC_UP+
STP
SunVTS
Tip
TPE
TOD
TTL
U2P
UPA
UPA AD 0
UPA AD 1
-4 Sun Ultra 80 Service Manual • March 2000
Pronounced "prom." An acronym for programmable read-only memory. A type
of read-only memory (ROM) that allows data to be written into the device with
hardware called a PROM programmer. After the PROM has been programmed,
it is dedicated to that data and cannot be reprogrammed.
RAM digital-to-analog converter. An ASIC responsible for direct interface to
3DRAM. Also provides on-board phase-lock loop (PLL) and clock generator
circuitry for the pixel clock.
Resistive-capacitive.
Reset, interrupt, scan, and clock. An ASIC responsible for reset, interrupt, scan,
and clock.
Single buffer.
Small computer system interface.
System controller uniprocessor plus. An ASIC that regulates the flow of
requests and data throughout the system unit.
Shielded twisted-pair.
A diagnostic application designed to test hardware.
A connection that enables a remote shell window to be used as a terminal to
display test data from a system.
Twisted-pair Ethernet.
Time of day. A timekeeping intergrated circuit.
Transistor-transistor logic.
UPA-to-PCI. An ASIC that controls the PCI buses. It forms the bridge from the
UPA bus to the PCI buses.
UltraSPARC port architecture. Provides processor-to-memory interconnection.
UPA address bus 0. Provides data interface between CPU module 0 and the
QSC ASIC.
UPA address bus 1. Provides data interface between CPU module 1 and the
QSC ASIC. Supports slave UPA connection to the expansion slot for graphics
capability.