Digital Specifications - Analog Devices AD9866 Instructions Manual

AD9866
Parameter
Rx Mode
I + I
AVDD CLKVDD
I + I
DVDD DRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER-DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
POWER-UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
1 Default power-up settings for MODE = LOW and CONFIG = LOW.
2
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP's current consumption, which is application dependent.

DIGITAL SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
Table 4.
Parameter
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
CMOS LOGIC OUTPUTS (C
LOAD
High Level Output Voltage (I
Low Level Output Voltage (I
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
RESET
Minimum Low Pulse Width (Relative to f
2
(I + I
AVDD
= 5 pF)
= 1 mA)
OH
= 1 mA)
OH
= 15 pF)
LOAD
= 15 pF)
LOAD
= 5 pF)
LOAD
= 5 pF)
LOAD
)
ADC
Temp Test Level
25°C
25°C
)
CLKVDD
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
Full IV
Full
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
= 2 kΩ, unless otherwise noted.
SET
Temp Test Level
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Rev. A | Page 6 of 48
Min Typ Max
225 253
36.5 39
87
108
38
10 120
170
107
1.66
13
440
12
20
20
27
7.8
88
13
20
20
Min Typ Max
DRVDD – 0.7
0.4
12
3
DRVDD – 0.7
0.4
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
W
mA
ns
ns
ns
ns
ns
µs
ns
µs
ns
µs
Unit
V
V
µA
pF
V
V
ns
ns
ns
ns
Clock
cycles