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2
I
C and SPI Buses
This section describes the MachXO3-9400 Development Board I
2
6.1. I
C Topology
The MachXO3-9400 Development Board has a flexible I
2
board. The global I
C bus has the signal names SDA0 and SCL0 and they are routed close to the devices and headers as
shown in
Figure
6.1.
Raspberry Pi
Header (JP3)
Versa Header
(X3)
The board provides two options for accessing the global I
(J11) through FTDI (U1) and the other is from the Aardvark header (JP2) for an Aardvark cable. Two analog MUXes, as
shown in
Figure
6.2, are used to select between the USB and Aardvark cables, both MUXes are controlled by the signal
USB_I2C_EN.
2
Table 6.1. I
C MUX Function
Global I
2
C
USB_I2C_EN
Controller
Logic Level
Aardvark
0 (JP10 removed)
Header
(JP2)
USB FTDI
1 (JP10 installed)
(U1)
When the jumper JP10 is removed, the USB_I2C_EN signal is low and the Aardvark header JP2 is connected to the
2
global I
C bus. When the jumper JP10 is installed, the USB_I2C_EN signal is high and the USB connector J11 is
2
connected to the global I
C bus through the FTDI device.
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0
2
C and SPI topology.
2
C bus to support all optional connectors and devices on the
Aardvark Header (JP2)
FTDI (UI)
2
I
C MUX (U10/U11)
ASC
MachXO3
(U7)
Bank3
R97
R98
MachXO3
MachXO3
Bank0
Bank4
2
Figure 6.1. I
C Topology
2
C bus from external cables. One is from the mini USB cable
FSA4157 MUX
SCL0 Test Point
Function
JP2_SCL <> SCL0
Pin1 of JP2
JP2_SDA <> SDA0
FTDI_SCL <> SCL0
FTDI_SDA <> SDA0
MachXO3-9400 Development Board
Evaluation Board User Guide
MachXO3
FX12 Headers
Bank2
Arduino
MachXO3
Header (J2)
Bank1
SDA0 Test Point
Pin3 of JP2
TP1
TP2
(U4/U5)
23
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