Spi Flash - Lattice Semiconductor LatticeMico32/DSP User Manual

Lattice Semiconductor
Table 24. Interface Between the MachXO and the FPGA
MachXO Pin
A1
A3
A4
A5
FPGA
The LFECP33 represents the heart of the board. It has the following features:
• 32.8 k Look-Up Tables (LUTs)
• 131 kbit distributed RAM
• 498 kbit EBR SRAM
• 54 EBR SRAM blocks
• Four PLLs
• 360 user I/Os available
• DDR memory support (DDR400)
• Supported I/O standards: LVCMOS, LVTTL, SSTL, HSTL, LVDS
The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDL
design entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software.
Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards.
Select FPGA/FPSC Boards -> LatticeMico32/DSP Development board and click on the Design Files link.
For further information please consult the LatticeECP/EC Family Data Sheet.
Parallel Flash
Two parallel MX29LV128MBTI-90Q Flash components from Macronics are provided on the board for program code
and data. As with the SRAM, a 32-bit data bus is realized with these two devices. Thus, Flash can be accessed as
a 8Mx32 memory. The 23-bit address bus, the data bus and the control signals are connected directly to the FPGA.

SPI Flash

The LatticeECP33 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to be
automatically configured upon power-up, a non-volatile 8 Mbit SPI Flash device is provided. The SPI Flash can be
programmed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWN-
LOAD connector or via the integrated USB configuration interface.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the
board inoperable.
To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. The
FPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices.
The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device.
Configure the SPI Flash as follows:
1. In the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box.
Signal Name MachXO Pin
MACHXO IO0 C1
MACHXO IO2 F3
MACHXO IO4 U3
MACHXO IO6 V2
LatticeMico32/DSP Development Board
MachXO Pin Signal Name
A2 MACHXO IO1
B3 MACHXO IO3
C4 MACHXO IO5
C8 MACHXO CLK
21
User's Guide
MachXO Pin
E2
R6
V3
B1