Espressif Systems ESP32 Technical Reference Manual page 89

6.4 Registers
31 30 29 28 27 26 25
0 0 0 0 0 0 0
RMT_CHn_TX_THR_EVENT_INT_ENA The
RMT_CHn_TX_THR_EVENT_INT
RMT_CHn_ERR_INT_ENA The interrupt enable bit for the RMT_CHn_ERROR_INT interrupt. (R/W)
RMT_CHn_RX_END_INT_ENA The interrupt enable bit for the
(R/W)
RMT_CHn_TX_END_INT_ENA The interrupt enable bit for the
(R/W)
31 30 29 28 27 26 25
0 0 0 0 0 0 0
RMT_CHn_TX_THR_EVENT_INT_CLR Set this bit to clear the
terrupt. (WO)
RMT_CHn_ERR_INT_CLR Set this bit to clear the RMT_CHn_ERRINT interrupt. (WO)
RMT_CHn_RX_END_INT_CLR Set this bit to clear the
RMT_CHn_TX_END_INT_CLR Set this bit to clear the
Espressif Systems
Register 6.5: RMT_INT_ENA_REG (0x00a8)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
interrupt. (R/W)
Register 6.6: RMT_INT_CLR_REG (0x00ac)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
6 REMOTE CONTROLLER PERIPHERAL
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
interrupt enable
RMT_CHn_RX_END_INT
RMT_CHn_TX_END_INT
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
RMT_CHn_TX_THR_EVENT_INT
RMT_CHn_RX_END_INT
RMT_CHn_TX_END_INT
88 ESP32 Technical Reference Manual V1.0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
bit for
interrupt.
interrupt.
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
interrupt. (WO)
interrupt. (WO)
0
0 Reset
the
0
0 Reset
in-