Espressif Systems ESP32 Technical Reference Manual page 107

8.4 Registers
31
0 0 0 0 0 0 0
TIMGn_Tx_INT_WDT_INT_RAW The raw interrupt status bit for the
rupt. (RO)
TIMGn_Tx_INT_T1_INT_RAW The raw interrupt status bit for the
(RO)
TIMGn_Tx_INT_T0_INT_RAW The raw interrupt status bit for the
(RO)
31
0 0 0 0 0 0 0
TIMGn_Tx_INT_WDT_INT_ST The masked interrupt status bit for the
terrupt. (RO)
TIMGn_Tx_INT_T1_INT_ST The masked interrupt status bit for the
(RO)
TIMGn_Tx_INT_T0_INT_ST The masked interrupt status bit for the
(RO)
Espressif Systems
Register 8.19: TIMGn_Tx_INT_RAW_REG (0x009c)
0 0 0 0 0 0 0 0
Register 8.20: TIMGn_Tx_INT_ST_REG (0x00a0)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
TIMGn_Tx_INT_WDT_INT
TIMGn_Tx_INT_T1_INT
TIMGn_Tx_INT_T0_INT
0 0 0 0 0 0 0 0
TIMGn_Tx_INT_T1_INT
TIMGn_Tx_INT_T0_INT
106 ESP32 Technical Reference Manual V1.0
8 64-BIT TIMERS
3 2 1
0 0 0 0 0 0 0 0
inter-
interrupt.
interrupt.
3 2 1
0 0 0 0 0 0 0 0
TIMGn_Tx_INT_WDT_INT
interrupt.
interrupt.
0
0 Reset
0
0
Reset
in-