Espressif Systems ESP32 Technical Reference Manual page 79

5.4 Registers
31
0 0 0 0 0 0 0
LEDC_DUTY_CHNG_END_LSCHn_INT_RAW The
LEDC_DUTY_CHNG_END_LSCHn_INT
LEDC_DUTY_CHNG_END_HSCHn_INT_RAW The
LEDC_DUTY_CHNG_END_HSCHn_INT
LEDC_LSTIMERx_OVF_INT_RAW The raw interrupt status bit for the
interrupt. (RO)
LEDC_HSTIMERx_OVF_INT_RAW The raw interrupt status bit for the
interrupt. (RO)
31
0 0 0 0 0 0 0
LEDC_DUTY_CHNG_END_LSCHn_INT_ST The
LEDC_DUTY_CHNG_END_LSCHn_INT
LEDC_DUTY_CHNG_END_HSCHn_INT_ST The
LEDC_DUTY_CHNG_END_HSCHn_INT
LEDC_LSTIMERx_OVF_INT_ST The masked interrupt status bit for the
interrupt. (RO)
LEDC_HSTIMERx_OVF_INT_ST The masked interrupt status bit for the
interrupt. (RO)
Espressif Systems
Register 5.15: LEDC_INT_RAW_REG (0x0180)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
interrupt. (RO)
interrupt. (RO)
Register 5.16: LEDC_INT_ST_REG (0x0184)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
interrupt. (RO)
interrupt. (RO)
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
raw interrupt
raw interrupt
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
masked interrupt
masked interrupt
78 ESP32 Technical Reference Manual V1.0
5 LED_PWM
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
status bit for
status bit for
LEDC_LSTIMERx_OVF_INT
LEDC_HSTIMERx_OVF_INT
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
status bit for
status bit for
LEDC_LSTIMERx_OVF_INT
LEDC_HSTIMERx_OVF_INT
0
0 Reset
the
the
0
0
Reset
the
the