Espressif Systems ESP32 Technical Reference Manual page 104

8.4 Registers
31
TIMGn_TxLOAD_REG Write any value to trigger a timer
TIMGn_Tx_WDT_EN When set, MWDT is enabled. (R/W)
TIMGn_Tx_WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
(R/W)
TIMGn_Tx_WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
(R/W)
TIMGn_Tx_WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
(R/W)
TIMGn_Tx_WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
(R/W)
TIMGn_Tx_WDT_EDGE_INT_EN When set, an edge type interrupt will be generated on timeout of a
stage configured to generate an interrupt. (R/W)
TIMGn_Tx_WDT_LEVEL_INT_EN When set, a level type interrupt will be generated on timeout of a
stage configured to generate an interrupt. (R/W)
TIMGn_Tx_WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
TIMGn_Tx_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
TIMGn_Tx_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W)
Espressif Systems
Register 8.9: TIMGn_TxLOAD_REG (x: 0-1) (0x20+0x24*x)
0x000000000
Register 8.10: TIMGn_Tx_WDTCONFIG0_REG (0x0048)
31 30 29 28 27 26 25 24
0 0 0 0 0
x time-base counter reload. (WO)
23 22 21 20 18 17
0 0 0x1 0x1
103 ESP32 Technical Reference Manual V1.0
8 64-BIT TIMERS
15 14
1 Reset
0
Reset