Reset And Clock; System Reset; Introduction; Reset Source - Espressif Systems ESP32 Technical Reference Manual

3. Reset and Clock

3.1 System Reset

3.1.1 Introduction

The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the
RAM. Figure 4 shows the subsystems included in each reset level.
• CPU reset: Only resets the registers of one or both the CPU cores.
• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is
not reset.
• System reset: Resets all the registers on the chip, including those of the RTC.

3.1.2 Reset Source

While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to
reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU
reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in
APP_CNTL_RESET_CAUSE_PROCPU. Table
these registers.
PRO APP Source
0x01 0x01 Chip Power On Reset
0x10 0x10 RWDT System Reset
0x0F 0x0F Brown Out Reset
0x03 0x03 Software System Reset
0x05 0x05 Deep Sleep Rest
0x07 0x07 MWDT0 Global Reset
Espressif Systems
Figure 4: System Reset
8 shows the possible reset reason values that can be read from
Table 8: PRO_CPU and APP_CPU reset reason values
Reset Type

System Reset

System Reset
System Reset
Core Reset
Core Reset
Core Reset
Note
-
Refer to WDT Chapter.
Refer to Power Management Chapter.
Configure RTC_CNTL_SW_SYS_RST register.
Refer to Power Management Chapter.
Refer to WDT Chapter.
22 ESP32 Technical Reference Manual V1.0
3 RESET AND CLOCK