Espressif Systems ESP32 Technical Reference Manual page 5

6.2.5 Receiver
6.2.6 Interrupts
6.3 Register Summary
6.4 Registers
7 PULSE_CNT
7.1 Introduction
7.2 Functional Description
7.2.1 Architecture
7.2.2 Counter Channel Inputs
7.2.3 Watchpoints
7.2.4 Examples
7.2.5 Interrupts
7.3 Register Summary
7.4 Registers
8 64-bit Timers
8.1 Introduction
8.2 Functional Description
8.2.1 16-bit Prescaler
8.2.2 64-bit Time-base Counter
8.2.3 Alarm Generation
8.2.4 MWDT
8.2.5 Interrupts
8.3 Register summary
8.4 Registers
9 Watchdog Timers
9.1 Introduction
9.2 Features
9.3 Functional Description
9.3.1 Clock
9.3.1.1 Operating Procedure
9.3.1.2 Write Protection
9.3.1.3 Flash Boot Protection
9.3.1.4 Registers
10 AES Accelerator
10.1 Introduction
10.2 Features
10.3 Functional Description
10.3.1 AES Algorithm Operations
10.3.2 Key, Plaintext and Ciphertext
10.3.3 Endianness
10.3.4 Encryption and Decryption Operations
10.3.5 Speed
10.4 Register summary
83
83
84
85
90
90
90
90
90
91
92
92
92
94
98
98
98
98
98
99
99
99
99
101
108
108
108
108
108
109
109
109
110
111
111
111
111
111
111
112
114
114
114