Espressif Systems ESP32 Technical Reference Manual page 74

5.4 Registers
Register 5.5: LEDC_HSCHn_DUTY_R_REG (n: 0-7) (0x2C+0x10*n)
31 25
0x00
LEDC_DUTY_HSCHn_R This register represents the current duty cycle of the output signal for high-
speed channel n. (RO)
Register 5.6: LEDC_LSCHn_CONF0_REG (n: 0-7) (0xBC+0x10*n)
31
LEDC_PARA_UP_LSCHn
LEDC_LSCHn_DUTY for low-speed channel n. (R/W)
LEDC_IDLE_LV_LSCHn
inactive. (R/W)
LEDC_SIG_OUT_EN_LSCHn
LEDC_TIMER_SEL_LSCHn
them for low-speed channel n. (R/W)
0: select lstimer0;
1: select lstimer1;
2: select lstimer2;
3: select lstimer3.
Espressif Systems
24
0x0000000
This bit is used to update register LEDC_LSCHn_HPOINT and
This bit is used to control the output value when low-speed channel
This is the output enable control bit for low-speed channel n. (R/W)
There are four low speed timers, the two bits are used to select one of
0x0000000
73 ESP32 Technical Reference Manual V1.0
5 LED_PWM
0
Reset
5 4 3 2 1 0
0 0 0 0
Reset
n is