Memory Speed - Espressif Systems ESP32 Technical Reference Manual

1.3 Functional Description 1 SYSTEM AND MEMORY

1.3.4.3 Memory Speed

The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can access the SRAM at full
speed and simultaneously, provided they access address different memory banks.
Espressif Systems 16 ESP32 Technical Reference Manual V1.0