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Espressif Systems ESP32 Hardware Design Manuallines

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ESP32
Hardware Design Guidelines
Release master
Espressif Systems
Dec 25, 2023

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Summary of Contents for Espressif Systems ESP32

  • Page 1 ESP32 Hardware Design Guidelines Release master Espressif Systems Dec 25, 2023...

  • Page 2: Table Of Contents

    Table of contents Table of contents 1 About This Document Introduction ..........Latest Version of This Document .
  • Page 3 ......... . . 32 4.11.3 3. When ESP32 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor.
  • Page 4 Table of contents This document provides guidelines for the ESP32 SoC. Espressif Systems Release master Submit Document Feedback...
  • Page 5 Table of contents Espressif Systems Release master Submit Document Feedback...

  • Page 6: About This Document

    Espressif’s standards. The guidelines are intended for hardware and application engineers. The document assumes that you possess a certain level of familiarity with the ESP32 SoC. In case you lack prior knowledge, we recommend utilizing this document in conjunction with the ESP32 Series Datasheet.
  • Page 7 Chapter 1. About This Document Espressif Systems Release master Submit Document Feedback...

  • Page 8: Product Overview

    • SDIO Wi-Fi + Bluetooth Networking Card • Touch and Proximity Sensing For more information about ESP32, please refer to ESP32 Series Datasheet. Note: Unless otherwise specified,“ESP32”used in this document refers to the series of chips, instead of a specific chip variant.
  • Page 9 Chapter 2. Product Overview Espressif Systems Release master Submit Document Feedback...

  • Page 10: Schematic Checklist

    The integrated circuitry of ESP32 requires only 20 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32.

  • Page 11: Power Supply

    3.1.1 Digital Power Supply ESP32 has pin37 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 1.8 V ~ 3.6 V. It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).

  • Page 12: Analog Power Supply

    3.1.2 Analog Power Supply ESP32’s VDDA and VDD3P3 pins are the analog power supply pins, working at 2.3 V ~ 3.6 V. For VDD3P3, when ESP32 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse.
  • Page 13 Chapter 3. Schematic Checklist Fig. 5: ESP32 Schematic for VDD_SDIO Pin Powered by External Supply Fig. 6: ESP32 Schematic for Analog Power Supply Pins Espressif Systems Release master Submit Document Feedback...

  • Page 14: Rtc Power Supply

    ESP32’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low. When ESP32 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been brought up.

  • Page 15: Flash And Psram

    – Implementing reset functionality through a button or the main controller. 3.3 Flash and PSRAM ESP32 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off- package RAM is optional. 3.3.1 In-Package Flash and PSRAM The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM.

  • Page 16: Off-Package Flash And Psram

    3.3.2 Off-Package Flash and PSRAM ESP32 supports up to 16 MB off-package flash and 8 MB off-package RAM. If VDD_SDIO is used to supply power, make sure to select the appropriate off-package flash and RAM according to the power voltage on VDD_SDIO (1.8 V/3.3 V).

  • Page 17: Rtc Clock Source (Optional)

    3.4.2 RTC Clock Source (Optional) ESP32 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock. The external RTC clock source enhances timing accuracy and consequently decreases average power consumption, without impacting functionality.

  • Page 18: Rf Circuit

    3.5 RF 3.5.1 RF Circuit ESP32’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements: • For the RF traces on the PCB board, 50 Ω impedance control is required.

  • Page 19: Rf Tuning

    ESP32 RF Tuning Diagram shows the general process of RF tuning. Fig. 13: ESP32 RF Tuning Diagram The initial value of the parameters in the matching network can be 0 Ω. The recommended value of S11 is 25+j0. The recommended central frequency is 2442 MHz.

  • Page 20: Strapping Pins

    These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal function pins. All the information about strapping pins is covered in ESP32 Series Datasheet > Section Strapping Pins. In this document, we will mainly cover the strapping pins related to boot mode.

  • Page 21: Gpio

    3.8 GPIO The pins of ESP32 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configurations, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about IO...

  • Page 22: Adc

    CAP1. C5 (10 nF) that connects to CAP1 should be of 10% tolerance and is required for proper operation of ESP32. RC circuit between CAP1 and CAP2 pins may be omitted under certain conditions. This circuit is used when entering Deep-sleep mode.

  • Page 23: Sdio

    Fig. 15: ESP32 Schematic for External Capacitor 3.11 SDIO There are two sets of GPIOs (slot0 and slot1) that can be assigned to SDIO on ESP32, as shown in Table SDIO Pin Configuration. When ESP32 works as an SDIO host or slave, connect GPIOs in slot1 to signal lines.

  • Page 24: Pcb Layout Design

    Chapter 4 PCB Layout Design This chapter introduces the key points of how to design an ESP32 PCB layout using an ESP32 module (see Figure ESP32 Reference PCB Layout) as an example. Fig. 1: ESP32 Reference PCB Layout 4.1 General Principles of PCB Layout It is recommended to use a four-layer PCB design: •...

  • Page 25: Positioning A Module On A Base Board

    Fig. 2: Placement of ESP32 Modules on Base Board (antenna feed point on the right) If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna area (no copper, routing, or components on it), and place the feed point of the antenna closest to the board.

  • Page 26: Power Supply

    Chapter 4. PCB Layout Design Fig. 3: Keepout Zone for ESP32 Module’s Antenna on the Base Board 4.3 Power Supply Figure ESP32 Power Traces in a Four-layer PCB Design shows the overview of the power traces in a four-layer PCB design.

  • Page 27: Power Layout

    4.4 Crystal Figure ESP32 Crystal Layout (with Keep-out Area on Top Layer) shows a reference PCB layout where the crystal is connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground isolation.
  • Page 28 Chapter 4. PCB Layout Design Fig. 5: ESP32 Power Traces in a Two-layer PCB Design Fig. 6: ESP32 Crystal Layout (with Keep-out Area on Top Layer) Espressif Systems Release master Submit Document Feedback...

  • Page 29: Rf Layout On Four-Layer Pcb

    ESP32 RF Layout in a Four-layer PCB Design. Fig. 7: ESP32 RF Layout in a Four-layer PCB Design The RF layout should meet the following guidelines: • A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
  • Page 30 Chapter 4. PCB Layout Design Fig. 8: ESP32 PCB Stack-up Design Fig. 9: ESP32 Stub in a Four-layer PCB Design Espressif Systems Release master Submit Document Feedback...

  • Page 31: Rf Layout On Two-Layer Pcb

    PCB layers. Other good practices for routing RF traces in four-layer PCB designs still apply to two-layer board designs. Fig. 10: ESP32 RF Layout in a Two-layer PCB Design 4.6 Flash and PSRAM The layout for flash and PSRAM should follow the guidelines below: •...

  • Page 32: Uart

    Chapter 4. PCB Layout Design Fig. 11: ESP32 Flash and PSRAM Layout 4.8 UART Figure ESP32 UART Layout shows the UART layout. Fig. 12: ESP32 UART Layout The UART layout should meet the following guidelines: • The series resistor on the U0TXD trace needs to be placed close to the chip side and away from the crystal.

  • Page 33: Touch Sensor

    4.10 Touch Sensor ESP32 offers up to 10 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows to use touch pads with smaller area to implement the touch detection function.
  • Page 34 Chapter 4. PCB Layout Design Fig. 14: ESP32 Electrode Pattern Requirements Fig. 15: ESP32 Sensor Track Routing Requirements Espressif Systems Release master Submit Document Feedback...

  • Page 35: Typical Layout Problems And Solutions

    Analysis: The voltage ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be tested when ESP32 is in the normal working mode. The ripple increases when the power gets high in a different mode.

  • Page 36: Hardware Development

    To review module reference designs please check the Documentation section on Espressif’s official website. 5.2 ESP32 Development Boards For a list of the latest designs of ESP32 boards please check the Development Boards section on Espressif’s official website. 5.3 Download Guidelines You can download firmware to ESP32 via UART.
  • Page 37 Chapter 5. Hardware Development Espressif Systems Release master Submit Document Feedback...

  • Page 38: Related Documentation And Resources

    Chapter 6 Related Documentation and Resources • Chip Datasheet (PDF) • Technical Reference Manual (PDF) • Chip Errata (PDF) • Chip Variants • Modules • Development Boards • Espressif KiCad Library • ESP Product Selector • Regulatory Certificates • User Forum (Hardware) •...
  • Page 39 Chapter 6. Related Documentation and Resources Espressif Systems Release master Submit Document Feedback...

  • Page 40: Glossary

    Chapter 7 Glossary The glossary contains terms and acronyms that are used in this document. Term Description Capacitor-Inductor-Capacitor DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory Electrostatic Discharge Inductor-Capacitor Power Amplifier Resistor-Capacitor Real-Time Clock Zero-ohm resistor A zero-ohm resistor is a placeholder on the circuit so that another higher ohm resistor can replace it, depending on design cases.
  • Page 41 Chapter 7. Glossary Espressif Systems Release master Submit Document Feedback...

  • Page 42: Revision History

    Chapter 8 Revision History 8.1 ESP Hardware Design Guidelines v1.0 This is the first version of the ESP Hardware Design Guidelines in HTML format. During the migration from PDF to HTML format, minor updates, improvements, and clarifications were made throughout the documentation. If you would like to check previous versions of the document, please submit documentation feedback.
  • Page 43 Chapter 8. Revision History Espressif Systems Release master Submit Document Feedback...

  • Page 44: Disclaimer And Copyright Notice

    Chapter 9 Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy. No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose, nor does any warranty otherwise arising out of any proposal, specification or sample.

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