Espressif Systems ESP32 Technical Reference Manual page 50

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4.13 Registers
31
0
0
0
0
0
0
0
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status. (R/W)
31
0
0
0
0
0
0
0
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is one in the
value that is written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (RO)
31
0
0
0
0
0
0
0
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is one in
the value that is written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared.
(RO)
31
x
x
x
x
x
x
x
GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)
Espressif Systems
Register 4.19: GPIO_STATUS1_REG (0x0050)
0
0
0
0
0
0
0
0
Register 4.20: GPIO_STATUS1_W1TS_REG (0x0054)
0
0
0
0
0
0
0
0
Register 4.21: GPIO_STATUS1_W1TC_REG (0x0058)
0
0
0
0
0
0
0
0
Register 4.22: GPIO_ACPU_INT_REG (0x0060)
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
49
ESP32 Technical Reference Manual V1.0
4 IO_MUX AND GPIO MATRIX
8
7
0
x
x
x
x
x
x
x
8
7
0
x
x
x
x
x
x
x
8
7
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
Reset
0
x
Reset
0
x
Reset
0
x
Reset

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