Espressif Systems ESP32 Technical Reference Manual page 101

8.3 Register summary
Name
Timer 1 configuration and control registers
TIMGn_T1CONFIG_REG
TIMGn_T1LO_REG
TIMGn_T1HI_REG
TIMGn_T1UPDATE_REG
TIMGn_T1ALARMLO_REG
TIMGn_T1ALARMHI_REG
TIMGn_T1LOADLO_REG
TIMGn_T1LOAD_REG
System watchdog timer configuration and control registers
TIMGn_Tx_WDTCONFIG0_REG
TIMGn_Tx_WDTCONFIG1_REG
TIMGn_Tx_WDTCONFIG2_REG
TIMGn_Tx_WDTCONFIG3_REG
TIMGn_Tx_WDTCONFIG4_REG
TIMGn_Tx_WDTCONFIG5_REG
TIMGn_Tx_WDTFEED_REG
TIMGn_Tx_WDTWPROTECT_REG
Interrupt registers
TIMGn_Tx_INT_RAW_REG
TIMGn_Tx_INT_ST_REG
TIMGn_Tx_INT_ENA_REG
TIMGn_Tx_INT_CLR_REG
Espressif Systems
Description
Timer 1 configuration register
Timer 1 current value, low 32 bits
Timer 1 current value, high 32 bits
Write to copy current timer value to
TIMGn_T1_(LO/HI)_REG
Timer 1 alarm value, low 32 bits
Timer 1 alarm value, high 32 bits
Timer 1 reload value, low 32 bits
Write to reload timer
TIMGn_T1_(LOADLOLOADHI)_REG
Watchdog timer configuration register
Watchdog timer prescaler register
Watchdog timer stage 0 timeout value
Watchdog timer stage 1 timeout value
Watchdog timer stage 2 timeout value
Watchdog timer stage 3 timeout value
Write to feed the watchdog timer
Watchdog write protect register
Raw interrupt status
Masked interrupt status
Interrupt enable bits
Interrupt clear bits
100
8 64-BIT TIMERS
TIMG0 TIMG1
0x3FF5F024 0x3FF60024 R/W
0x3FF5F028 0x3FF60028 RO
0x3FF5F02C 0x3FF6002C RO
0x3FF5F030 0x3FF60030 WO
0x3FF5F034 0x3FF60034 R/W
0x3FF5F038 0x3FF60038 R/W
0x3FF5F03C 0x3FF6003C R/W
from
0x3FF5F044 0x3FF60044 WO
0x3FF5F048 0x3FF60048 R/W
0x3FF5F04C 0x3FF6004C R/W
0x3FF5F050 0x3FF60050 R/W
0x3FF5F054 0x3FF60054 R/W
0x3FF5F058 0x3FF60058 R/W
0x3FF5F05C 0x3FF6005C R/W
0x3FF5F060 0x3FF60060 WO
0x3FF5F064 0x3FF60064 R/W
0x3FF5F09C 0x3FF6009C RO
0x3FF5F0A0 0x3FF600A0 RO
0x3FF5F098 0x3FF60098 R/W
0x3FF5F0A4 0x3FF600A4 WO
ESP32 Technical Reference Manual V1.0
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