Data Structure - Espressif Systems ESP32 Technical Reference Manual

6.2 Functional Description 6 REMOTE CONTROLLER PERIPHERAL
6.2.2 RMT RAM
Figure 15: Data Structure
The data structure in RAM is shown in Figure 15. Each 32-bit value contains two 16-bit entries, containing two
fields each: "level" indicates whether a high-level or a low-level value is to be sent or was received, "period" is the
duration (in channel clock periods) for which the level lasts. A period of zero is interpreted as an end marker: the
transmitter will stop transmitting once it has read this and the receiver will write this once it has detected that the
signal it received has gone idle.
Normally, only one block of 64x32-bit worth of data can be sent or received. If the data size is larger than this
block size, blocks can either be extended or the channel can be configured for wraparound mode.
The RMT RAM can be accessed via APB bus. The initial address is RMT base address + 0x800. The RAM block
is divided into eight 64x32-bit blocks. By default, each channel uses one block (block 0 for channel 0, block 1 for
channel 1, and so on). Users can extend the memory for a specific channel by configuring RMT_MEM_SIZE_CHn
register; setting this to >1 will make the channel also use the memory of subsequent channels. The RAM address
range for channel n is start_addr_CHn to end_addr_CHn, which are defined by:
= RMT base address + 0x800 + 64 ∗ 4 ∗ n, and
start_addr_chn
= RMT base address + 0x800 + 64 ∗ 4 ∗ + 64 ∗ 4 ∗ mod 512 ∗ 4
end_addr_chn n RMT_MEM_SIZE_CHn
To protect a receiver from overwriting the blocks a transmitter is about to transmit, RMT_MEM_OWNER_CHn
can be configured to assign the owner, i.e. transmitter or receiver, of channel n's RAM block. If this ownership is
violated, the RMT_CHn_ERR interrupt will be generated.
6.2.3 Clock
The main clock for a channel is generated by taking either the 80 MHz APB clock or REF_TICK (usually 1MHz),
according to the state of RMT_REF_ALWAYS_ON_CHn. For more information on the clock sources, please refer
to Chapter Reset And Clock. This gets then scaled down using a configurable 8-bit divider to create the channel
clock, to be used by both the carrier wave generator as well as by the counter. The divider value can be set by
configuring RMT_DIV_CNT_CHn.
6.2.4 Transmitter
When the RMT_TX_START_CHn register is 1, the transmitter of channel n will start reading data from RAM and
sending it. The transmitter will receive a 32-bits value each time it reads from RAM. Of these 32 bits, the low
16-bit entry is sent first, the high entry second.
To transmit more data than fits in the channels RAM, wraparound mode can be enabled. In this mode, when the
transmitter has reached the last entry in the channels memory, it will loop back to the first byte. To use this
mechanism to send more data than fits in the channels RAM, fill the RAM with the initial events and set
RMT_CHn_TX_LIM_REG to cause an RMT_CHn_TX_THR_EVENT_INT interrupt before the wraparound
Espressif Systems 82 ESP32 Technical Reference Manual V1.0