Peripheral Clock; Peripheral Clock Usage - Espressif Systems ESP32 Technical Reference Manual

3.2 System Clock
Clock Source SEL*
0 / XTL_CLK -
1 / PLL_CLK 0
1 / PLL_CLK 1
2 / RTC8M_CLK -
3 / APLL_CLK 0
3 / APLL_CLK 1
*SEL: DPORT_CPUPERIOD _SEL value

3.2.4 Peripheral Clock

Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK and PLL_D2_CLK.
Table 11 shows which clocks can be used by which peripherals.
Peripherals APB_CLK
EMAC Y
TIMG Y
I2S Y
UART Y
RMT Y
LED PWM Y
PWM Y
I2C Y
SPI Y
PCNT Y
Efuse Controller Y
SDIO Slave Y
SDMMC Y
3.2.4.1 APB_CLK Source
The APB_CLK is derived from CPU_CLK as detailed in Table 12. The division factor depends on the CPU_CLK
source.
Espressif Systems
Table 10: CPU_CLK Derivation
CPU Clock
CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0
CPU_CLK = PLL_CLK / 4
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
CPU_CLK frequency is 160 MHz
CPU_CLK = RTC8M_CLK / (APB_CTRL_PRE_DIV_CNT+1)
APB_CTRL_PRE_DIV_CNT range is 0
CPU_CLK = APLL_CLK / 4
CPU_CLK = APLL_CLK / 2
Table 11: Peripheral Clock Usage
REF_TICK
N
N
N
Y
Y
Y
N
N
N
N
N
N
N
25
~ 1023. Default is 0.
~ 1023. Default is 0.
LEDC_SCLK APLL_CLK
N Y
N N
N Y
N N
N N
Y N
N N
N N
N N
N N
N N
N N
N N
ESP32 Technical Reference Manual V1.0
3 RESET AND CLOCK
PLL_D2_CLK
N
N
Y
N
N
N
N
N
N
N
N
N
N