Espressif Systems ESP32 Technical Reference Manual page 105

8.4 Registers
TIMGn_Tx_WDT_CLK_PRESCALE MWDT clock prescale value. MWDT clock period = 12.5 ns *
TIMGn_Tx_WDT_CLK_PRESCALE. (R/W)
31
TIMGn_Tx_WDTCONFIG2_REG Stage 0 timeout value, in MWDT clock cycles. (R/W)
31
TIMGn_Tx_WDTCONFIG3_REG Stage 1 timeout value, in MWDT clock cycles. (R/W)
31
TIMGn_Tx_WDTCONFIG4_REG Stage 2 timeout value, in MWDT clock cycles. (R/W)
31
TIMGn_Tx_WDTCONFIG5_REG Stage 3 timeout value, in MWDT clock cycles. (R/W)
Espressif Systems
Register 8.11: TIMGn_Tx_WDTCONFIG1_REG (0x004c)
31
0x00001
Register 8.12: TIMGn_Tx_WDTCONFIG2_REG (0x0050)
26000000
Register 8.13: TIMGn_Tx_WDTCONFIG3_REG (0x0054)
0x007FFFFFF
Register 8.14: TIMGn_Tx_WDTCONFIG4_REG (0x0058)
0x0000FFFFF
Register 8.15: TIMGn_Tx_WDTCONFIG5_REG (0x005c)
0x0000FFFFF
16
104 ESP32 Technical Reference Manual V1.0
8 64-BIT TIMERS
Reset
0
0
0
0
Reset
Reset
Reset
Reset