Espressif Systems ESP32 Technical Reference Manual page 88

6.4 Registers
31 30 29 28 27 26 25
0 0 0 0 0 0 0
RMT_CHn_TX_THR_EVENT_INT_RAW The
RMT_CHn_TX_THR_EVENT_INT
RMT_CHn_ERR_INT_RAW The raw interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO)
RMT_CHn_RX_END_INT_RAW The raw interrupt status bit for the
rupt. (RO)
RMT_CHn_TX_END_INT_RAW The raw interrupt status bit for the
(RO)
31 30 29 28 27 26 25
0 0 0 0 0 0 0
RMT_CHn_TX_THR_EVENT_INT_ST The
RMT_CHn_TX_THR_EVENT_INT
RMT_CHn_ERR_INT_ST The masked interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO)
RMT_CHn_RX_END_INT_ST The masked interrupt status bit for the
rupt. (RO)
RMT_CHn_TX_END_INT_ST The masked interrupt status bit for the
rupt. (RO)
Espressif Systems
Register 6.3: RMT_INT_RAW_REG (0x00a0)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
interrupt. (RO)
Register 6.4: RMT_INT_ST_REG (0x00a4)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
interrupt. (RO)
6 REMOTE CONTROLLER PERIPHERAL
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
raw interrupt
RMT_CHn_RX_END_INT
RMT_CHn_TX_END_INT
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
masked interrupt
87 ESP32 Technical Reference Manual V1.0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
status bit for
interrupt.
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
status bit for
RMT_CHn_RX_END_INT
RMT_CHn_TX_END_INT
0
0 Reset
the
inter-
0
0 Reset
the
inter-
inter-