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Espressif Systems ESP32 Technical Reference Manual

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ESP32 Technical Reference Manual
Espressif Systems
August 31, 2016

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Summary of Contents for Espressif Systems ESP32

  • Page 1 ESP32 Technical Reference Manual Espressif Systems August 31, 2016...

  • Page 2: Internal Rom

    About This Manual ESP32 Technical Reference Manual targets application developers. The manual provides detailed and complete information on how to use the ESP32 memory and peripherals. Release Notes Date Version Release notes 2016.08 V1.0 Initial release. Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice.

  • Page 3: Table Of Contents

    Contents 1 System and Memory Introduction Features Functional Description 1.3.1 Address Mapping 1.3.2 Embedded Memory 1.3.2.1 Internal ROM 0 1.3.2.2 Internal ROM 1 1.3.2.3 Internal SRAM 0 1.3.2.4 Internal SRAM 1 1.3.2.5 Internal SRAM 2 1.3.2.6 1.3.2.7 RTC FAST Memory 1.3.2.8 RTC SLOW Memory 1.3.3...
  • Page 4 3.2.4.6 Clock Source Considerations 3.2.5 Wi-Fi BT Clock 3.2.6 RTC Clock 4 IO_MUX and GPIO Matrix Introduction Peripheral Input via GPIO Matrix 4.2.1 Summary 4.2.2 Functional Description 4.2.3 Simple GPIO Input Peripheral Output via GPIO Matrix 4.3.1 Summary 4.3.2 Functional Description 4.3.3 Simple GPIO Output Direct I/O via IO_MUX...
  • Page 5 6.2.5 Receiver 6.2.6 Interrupts Register Summary Registers 7 PULSE_CNT Introduction Functional Description 7.2.1 Architecture 7.2.2 Counter Channel Inputs 7.2.3 Watchpoints 7.2.4 Examples 7.2.5 Interrupts Register Summary Registers 8 64-bit Timers Introduction Functional Description 8.2.1 16-bit Prescaler 8.2.2 64-bit Time-base Counter 8.2.3 Alarm Generation 8.2.4...
  • Page 6 10.5 Registers 11 SHA Accelerator 11.1 Introduction 11.2 Features 11.3 Functional Description 11.3.1 Padding and Parsing the Message 11.3.2 Message Digest 11.3.3 Hash Operation 11.3.4 Speed 11.4 Register Summary 11.5 Registers...
  • Page 7 List of Tables Address Mapping Embedded Memory Address Mapping Module with DMA External Memory Address Mapping Peripheral Address Mapping PRO_CPU, APP_CPU interrupt configuration CPU Interrupts PRO_CPU and APP_CPU reset reason values CPU_CLK Source CPU_CLK Derivation Peripheral Clock Usage APB_CLK Derivation REF_TICK Derivation LEDC_SCLK Derivation IO_MUX Light-sleep Pin Function Registers...
  • Page 8 System Clock IO_MUX, RTC IO_MUX and GPIO Matrix Overview Peripheral Input via IO_MUX, GPIO Matrix Output via GPIO Matrix ESP32 I/O Pad Power Sources LED_PWM Architecture LED_PWM High-speed Channel Diagram LED PWM Output Signal Diagram Output Signal Diagram of Gradient Duty Cycle...

  • Page 9: System And Memory

    1. System and Memory 1.1 Introduction The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs. With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning they use the same addresses to access the same memory.
  • Page 10 1.2 Features 1 SYSTEM AND MEMORY Figure block diagram illustrates the system structure, the block diagram in Figure illustrates the address map structure. Figure 1: System Structure Figure 2: System Address Mapping Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 11: Functional Description

    The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM. Table lists all embedded memories and their address ranges on the data and instruction buses. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 12: Internal Rom

    DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU, respectively. 1.3.2.2 Internal ROM 1 The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at address range 0x3FF9_0000 0x3FF9_FFFF of the data bus. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 13: Internal Sram

    0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000. Part of this memory can be remapped to the ROM 0 address space. See Internal Rom 0 for more information. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 14: Internal Sram

    CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an external physical memory address (in the external memory’s address space), according to the MMU settings. Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM. Espressif Systems...

  • Page 15: Peripherals

    External Flash Read 1.3.4 Peripherals The ESP32 has 41 peripherals. Table specifically describes the peripherals their respective address ranges. Almost all peripheral modules can be accessed by either CPU at the same address, the only exception being the PID Controller.

  • Page 16: Asymmetric Pid Controller Peripheral

    The three parts are accessed at the address ranges 0x3FF4_B000 3FF4_BFFF, 0x3FF5_5000 3FF5_5FFF and 0x3FF5_8000 3FF5_8FFF of each CPU’s data bus. Similar to other peripherals, access to this peripheral is identical for both CPUs. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 17: Memory Speed

    FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory. Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can access the SRAM at full speed and simultaneously, provided they access address different memory banks. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 18: Interrupt Matrix

    2.3 Functional Description 2.3.1 Peripheral Interrupt Source ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 6. 67 of 71 ESP32 peripheral interrupt sources can be allocated to either CPU. The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU.
  • Page 19 Table 6: PRO_CPU, APP_CPU interrupt configuration PRO_CPU APP_CPU Peripheral Interrupt Source Peripheral Interrupt Peripheral Interrupt Status Register Status Register Configuration Register Name Configuration Register Name Name PRO_MAC_INTR_MAP_REG MAC_INTR APP_MAC_INTR_MAP_REG PRO_MAC_NMI_MAP_REG MAC_NMI APP_MAC_NMI_MAP_REG PRO_BB_INT_MAP_REG BB_INT APP_BB_INT_MAP_REG PRO_BT_MAC_INT_MAP_REG BT_MAC_INT APP_BT_MAC_INT_MAP_REG PRO_BT_BB_INT_MAP_REG BT_BB_INT APP_BT_BB_INT_MAP_REG PRO_BT_BB_NMI_MAP_REG BT_BB_NMI...
  • Page 20 PRO_CPU APP_CPU Peripheral Interrupt Source Peripheral Interrupt Peripheral Interrupt Status Register Status Register Configuration Register Name Configuration Register Name Name PRO_SPI2_DMA_INT_MAP_REG SPI2_DMA_INT APP_SPI2_DMA_INT_MAP_REG PRO_SPI3_DMA_INT_MAP_REG SPI3_DMA_INT APP_SPI3_DMA_INT_MAP_REG PRO_WDG_INT_MAP_REG WDG_INT APP_WDG_INT_MAP_REG PRO_TIMER_INT1_MAP_REG TIMER_INT1 APP_TIMER_INT1_MAP_REG PRO_TIMER_INT2_MAP_REG TIMER_INT2 APP_TIMER_INT2_MAP_REG PRO_TG_T0_EDGE_INT_MAP_REG PRO_INTR_STATUS_REG_1 TG_T0_EDGE_INT APP_INTR_STATUS_REG_1 APP_TG_T0_EDGE_INT_MAP_REG PRO_TG_T1_EDGE_INT_MAP_REG TG_T1_EDGE_INT APP_TG_T1_EDGE_INT_MAP_REG...

  • Page 21: Cpu Interrupt

    2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU In this section: • Source_X stands for any particular peripheral interrupt source. • PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 22: Cpu Nmi Interrupt Mask

    2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source The current interrupt status of a peripheral interrupt source can be read via the bit value in PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n) as shown in the mapping in Table 6. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 23: Reset And Clock

    3. Reset and Clock 3.1 System Reset 3.1.1 Introduction The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the RAM. Figure shows the subsystems included in each reset level. Figure 4: System Reset •...

  • Page 24: System Clock

    DPORT_APPCPU_RESETTING register. 3.2 System Clock 3.2.1 Introduction The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can be configured to meet different requirements. Figure shows the system clock structure. Figure 5: System Clock Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 25: Clock Source

    3.2 System Clock 3 RESET AND CLOCK 3.2.2 Clock Source The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source. Specifically, the clock sources available are: • High Speed Clocks – PLL_CLK is an internal PLL clock with a frequency of 320 MHz.

  • Page 26: Peripheral Clock

    EMAC TIMG UART LED PWM PCNT Efuse Controller SDIO Slave SDMMC 3.2.4.1 APB_CLK Source The APB_CLK is derived from CPU_CLK as detailed in Table 12. The division factor depends on the CPU_CLK source. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 27 LEDC_APB_CLK_SEL Value LEDC_SCLK Source RTC8M_CLK APB_CLK 3.2.4.4 APLL_SCLK Source The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration registers. 3.2.4.5 PLL_D2_CLK Source PLL_D2_CLK is half the PLL_CLK frequency. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 28 SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK or RTC8M_D256_CLK FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from RTC8M_CLK. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 29 4.1 Introduction The ESP32 chip features 40 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.

  • Page 30: Peripheral Input Via Io_Mux, Gpio Matrix

    3. Configure the IO_MUX register for GPIO pad X: • Set the function field to GPIO. • Enable the input by setting the xx_FUN_IE bit. • Set xx_FUN_WPU and xx_FUN_WPD fields as desired to enable internal pull-up/pull-down resistors. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 31 2. Optionally, to enable open drain mode set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register. 3. Configure the I/O mux register for GPIO pad X: • Set the function field to GPIO. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 32 Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can only select from a limited number of functions. However, better high frequency digital performance will be maintained. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 33 Pins can have different functions when the ESP32 is in Light-sleep mode. If the GPIOxx_SLP_SEL bit in the IO_MUX register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32...
  • Page 34 4.8 I/O Pad Power Supply IO pad power supply is shown in Figure 9. Figure 9: ESP32 I/O Pad Power Sources • Pads marked blue are RTC pads that have their individual analog function and can also act as normal digital IO pads.
  • Page 35 I2S1O_BCK_in I2S1O_BCK_out I2S0O_WS_in I2S0O_WS_out I2S1O_WS_in I2S1O_WS_out I2S0I_BCK_in I2S0I_BCK_out I2S0I_WS_in I2S0I_WS_out I2CEXT0_SCL_in I2CEXT0_SCL_out I2CEXT0_SDA_in I2CEXT0_SDA_out pwm0_sync0_in sdio_tohost_int_out pwm0_sync1_in pwm0_out0a pwm0_sync2_in pwm0_out0b pwm0_f0_in pwm0_out1a pwm0_f1_in pwm0_out1b pwm0_f2_in pwm0_out2a pwm0_out2b pcnt_sig_ch0_in0 pcnt_sig_ch1_in0 pcnt_ctrl_ch0_in0 pcnt_ctrl_ch1_in0 pcnt_sig_ch0_in1 pcnt_sig_ch1_in1 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 36 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 37 I2S0I_DATA_in0 I2S0O_DATA_out0 I2S0I_DATA_in1 I2S0O_DATA_out1 I2S0I_DATA_in2 I2S0O_DATA_out2 I2S0I_DATA_in3 I2S0O_DATA_out3 I2S0I_DATA_in4 I2S0O_DATA_out4 I2S0I_DATA_in5 I2S0O_DATA_out5 I2S0I_DATA_in6 I2S0O_DATA_out6 I2S0I_DATA_in7 I2S0O_DATA_out7 I2S0I_DATA_in8 I2S0O_DATA_out8 I2S0I_DATA_in9 I2S0O_DATA_out9 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 38 I2S1O_DATA_out7 I2S1I_DATA_in8 I2S1O_DATA_out8 I2S1I_DATA_in9 I2S1O_DATA_out9 I2S1I_DATA_in10 I2S1O_DATA_out10 I2S1I_DATA_in11 I2S1O_DATA_out11 I2S1I_DATA_in12 I2S1O_DATA_out12 I2S1I_DATA_in13 I2S1O_DATA_out13 I2S1I_DATA_in14 I2S1O_DATA_out14 I2S1I_DATA_in15 I2S1O_DATA_out15 I2S1O_DATA_out16 I2S1O_DATA_out17 I2S1O_DATA_out18 I2S1O_DATA_out19 I2S1O_DATA_out20 I2S1O_DATA_out21 I2S1O_DATA_out22 I2S1O_DATA_out23 I2S0I_H_SYNC pwm3_out1h I2S0I_V_SYNC pwm3_out1l I2S0I_H_ENABLE pwm3_out2h I2S1I_H_SYNC pwm3_out2l Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 39 CLK_OUT2 GPIO3 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 EMAC_RX_CLK SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 40 4.11 RTC_MUX Pin List Table shows the RTC pins and how they correspond to GPIO pads: Table 18: RTC_MUX Pin Summary Analog Function RTC GPIO Num GPIO Num Pad Name SENSOR_VP ADC_H ADC1_CH0 SENSOR_CAPP ADC_H ADC1_CH1 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 41 0x3FF44030 GPIO_ENABLE1_W1TC_REG GPIO 0-31 output enable register1_W1TC_REG 0x3FF44034 GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable bit set register_REG 0x3FF44024 GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable bit clear register_REG 0x3FF44028 GPIO_ENABLE1_REG GPIO 32-39 output enable register_REG 0x3FF4402C Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 42 GPIO 32-39 PRO_CPU non-maskable interrupt GPIO_PCPU_NMI_INT1_REG 0x3FF44080 status_REG GPIO_PIN0_REG Configuration for GPIO pin 0_REG 0x3FF44088 GPIO_PIN1_REG Configuration for GPIO pin 1_REG 0x3FF4408C GPIO_PIN2_REG Configuration for GPIO pin 2_REG 0x3FF44090 GPIO_PIN38_REG Configuration for GPIO pin 38_REG 0x3FF44120 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 43 Configuration register for pad SD_DATA0 0x3FF53064 IO_MUX_SD_DATA1_REG Configuration register for pad SD_DATA1 0x3FF53068 IO_MUX_GPIO5_REG Configuration register for pad GPIO5 0x3FF5306C IO_MUX_GPIO18_REG Configuration register for pad GPIO18 0x3FF53070 IO_MUX_GPIO19_REG Configuration register for pad GPIO19 0x3FF53074 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 44 RTC configuration for pin 10_REG 0x3FF48014 RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11_REG 0x3FF48015 RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12_REG 0x3FF48016 RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13_REG 0x3FF48017 RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14_REG 0x3FF48018 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 45 32KHz crystal pads configuration register_REG 0x3FF48023 RTCIO_TOUCH_CFG_REG Touch sensor configuration register_REG 0x3FF48024 RTCIO_EXT_WAKEUP0_REG External wake up configuration register_REG 0x3FF4802F RTCIO_XTL_EXT_CTR_REG Crystal power down enable gpio source_REG 0x3FF48030 RTCIO_SAR_I2C_IO_REG RTC I2C pad selection_REG 0x3FF48031 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 46 GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is one in the value that is written here, the corresponding bit in GPIO_OUT_DATA will be cleared. (RO) Register 4.4: GPIO_OUT1_REG (0x0010) Reset GPIO_OUT_DATA GPIO32-39 output value. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 47 Register 4.9: GPIO_ENABLE_W1TC_REG (0x0028) Reset GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is one in the value that is written here, the corresponding bit in GPIO_ENABLE will be cleared. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 48 GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is one in the value that is written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (RO) Register 4.13: GPIO_STRAP_REG (0x0038) Reset GPIO_STRAPPING GPIO strapping results: boot_sel_chip[5:0]: MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 49 Register 4.18: GPIO_STATUS_W1TC_REG (0x004c) Reset GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is one in the value that is written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 50 GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is one in the value that is written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (RO) Register 4.22: GPIO_ACPU_INT_REG (0x0060) Reset GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 51 GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO) Register 4.26: GPIO_ACPU_INT1_REG (0x0074) Reset GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO) Register 4.27: GPIO_ACPU_NMI_INT1_REG (0x0078) Reset GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 52 4.13 Registers 4 IO_MUX AND GPIO MATRIX Register 4.28: GPIO_PCPU_INT1_REG (0x007c) Reset GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO) Register 4.29: GPIO_PCPU_NMI_INT1_REG (0x0080) Reset GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 53 GPIO_FUNCm_IN_SEL Selection control for peripheral input m. A value of 0-39 selects which of the 40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constant high input or 0x30 for a constant low input. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 54 GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. A value of s(0<=s<256) connects peripheral output to GPIO output n. A value of 256 selects bit of GPIO_DATA_REG and GPIO_ENABLE_REG as the output value and output enable. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 55 IO_x_MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W) Register 4.34: RTCIO_RTC_GPIO_OUT_REG (0x0000) Reset RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 56 RTCIO_RTC_GPIO_OUT will be cleared. (WO) Register 4.37: RTCIO_RTC_GPIO_ENABLE_REG (0x0003) Reset RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1 means this GPIO pad is output. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 57 RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1], etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT- CIO_RTC_GPIO_PINn_REG. 1 means there is corresponding interrupt, 0 means there is no in- terrupt. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 58 (WO) Register 4.43: RTCIO_RTC_GPIO_IN_REG (0x0009) Reset RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each bit represents pad input value, 1 for high level and 0 for low level. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 59 RTCIO_DIG_PAD_HOLD_REG Select which digital pads are on hold. 0 allows normal operation, 1 holds the pad. (R/W) Register 4.46: RTCIO_HALL_SENS_REG (0x001e) Reset RTCIO_HALL_XPD_HALL Power on hall sensor and connect to VP and VN. (R/W) RTCIO_HALL_PHASE Reverse the polarity of the hall sensor. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 60 RTCIO_SENSOR_SENSEn_SLP_SEL Sleep mode selection signal of the pad. Set to 1 to put the pad in sleep mode. (R/W) RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 61 RTCIO_ADC_ADCn_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 62 RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 63 RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 64 RTCIO_XTAL_X32P_SLP_OE Output enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_X32P_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W) RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 65 RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option. 0: tie low; 1: tie high. (R/W) RTCIO_TOUCH_PADn_XPD Touch sensor power on. (R/W) RTCIO_TOUCH_PADn_TO_GPIO Connect the RTC pad input to digital pad input, 0 is available. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 66 RTCIO_SAR_I2C_SDA_SEL Selects a different pad as the RTC I2C SDA signal. 0: use pad TOUCH_PAD[1]; 1: use pad TOUCH_PAD[3]. (R/W) RTCIO_SAR_I2C_SCL_SEL Selects a different pad as the RTC I2C SCL signal. 0: use pad TOUCH_PAD[1]; 1: use pad TOUCH_PAD[3]. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 67 There are also 4 low-speed clock modules for the low-speed channels, from which one l_timerx can be selected. Figure 11: LED_PWM High-speed Channel Diagram Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 68 LEDC_DUTY_HSCHn[24..4]. When this value is reached, the output is latched low. By using these two values, the relative phase and the duty cycle of the PWM output can be set. Figure illustrates this. Figure 12: LED PWM Output Signal Diagram Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 69 Configuration register 0 for high-speed channel 3 0x3FF5903C LEDC_HSCH4_CONF0_REG Configuration register 0 for high-speed channel 4 0x3FF59050 LEDC_HSCH5_CONF0_REG Configuration register 0 for high-speed channel 5 0x3FF59064 LEDC_HSCH6_CONF0_REG Configuration register 0 for high-speed channel 6 0x3FF59078 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 70 Current duty cycle for high-speed channel 6 0x3FF59088 LEDC_HSCH7_DUTY_R_REG Current duty cycle for high-speed channel 7 0x3FF5909C LEDC_LSCH0_DUTY_REG Initial duty cycle for low-speed channel 0 0x3FF590A8 LEDC_LSCH1_DUTY_REG Initial duty cycle for low-speed channel 1 0x3FF590BC Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 71 Low-speed timer 2 current counter value 0x3FF59154 LEDC_HSTIMER3_VALUE_REG Low-speed timer 3 current counter value 0x3FF5915C Interrupt registers LEDC_INT_RAW_REG Raw interrupt status 0x3FF59180 LEDC_INT_ST_REG Masked interrupt status 0x3FF59184 LEDC_INT_ENA_REG Interrupt enable bits 0x3FF59188 LEDC_INT_CLR_REG Interrupt clear bits 0x3FF5918C Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 72 2: select hstimer2; 3: select hstimer3. Register 5.2: LEDC_HSCHn_HPOINT_REG (n: 0-7) (0x20+0x10*n) 0x0000 0x000000 Reset LEDC_HPOINT_HSCHn The output value changes to high when htimerx(x=[0,3]) selected by high- speed channel has reached reg_hpoint_hschn[19:0]. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 73 This register is used to increase or decrease the duty cycle every REG_DUTY_CYCLE_HSCHn cycles for high-speed channel n. (R/W) LEDC_DUTY_SCALE_HSCHn This register is used to increase or decrease the step scale for high- speed channel n. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 74 There are four low speed timers, the two bits are used to select one of them for low-speed channel n. (R/W) 0: select lstimer0; 1: select lstimer1; 2: select lstimer2; 3: select lstimer3. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 75 The register is used to control output duty. When lstimerx(x=[0,3]) chosen by low-speed channel has reached reg_lpoint_lschn,the output signal changes to low. (R/W) reg_lpoint_lschn=(reg_hpoint_lschn[19:0]+reg_duty_lschn[24:4]) (1) reg_lpoint_lschn=(reg_hpoint_lschn[19:0]+reg_duty_lschn[24:4] +1) (2) See the Functional Description for more information on when (1) or (2) is chosen. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 76 This register is used to increase or decrease the step scale for low- speed channel n. (R/W) Register 5.10: LEDC_LSCHn_DUTY_R_REG (n: 0-7) (0xCC+0x10*n) 0x00 0x0000000 Reset LEDC_DUTY_LSCHn_R This register represents the current duty of the output signal for low-speed channel n. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 77 The counter range is [0,2**reg_hstimerx_lim], the maximum bit width for counter is 20. (R/W) Register 5.12: LEDC_HSTIMERx_VALUE_REG (x: 0-3) (0x144+8*x) 0x0000 Reset LEDC_HSTIMERx_CNT Software can read this register to get the current counter value of high-speed timer x. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 78 The counter range is [0,2**reg_lstimerx_lim], the max bit width for counter is 20. (R/W) Register 5.14: LEDC_LSTIMERx_VALUE_REG (x: 0-3) (0x164+8*x) 0x0000 Reset LEDC_LSTIMERx_CNT Software can read this register to get the current counter value of low-speed timer x. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 79 LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (RO) LEDC_DUTY_CHNG_END_HSCHn_INT_ST The masked interrupt status LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (RO) LEDC_LSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_LSTIMERx_OVF_INT interrupt. (RO) LEDC_HSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_HSTIMERx_OVF_INT interrupt. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 80 LEDC_DUTY_CHNG_END_LSCHn_INT_CLR Set this clear LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (WO) LEDC_DUTY_CHNG_END_HSCHn_INT_CLR Set this clear LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (WO) LEDC_LSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_LSTIMERx_OVF_INT interrupt. (WO) LEDC_HSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_HSTIMERx_OVF_INT interrupt. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 81 5.4 Registers 5 LED_PWM Register 5.19: LEDC_CONF_REG (0x0190) Reset LEDC_APB_CLK_SEL This bit is used to set the frequency of SLOW_CLK. (R/W) 0: 8 MHz; 1: 80 MHz. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 82: Rmt Architecture

    APB bus, as well as read by the transmitters and written by the receivers. The transmitted signal can optionally be modulated by a carrier wave. Each channel is clocked by a divided-down signal derived from either the APB bus clock or REF_TICK. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 83: Data Structure

    To use this mechanism to send more data than fits in the channels RAM, fill the RAM with the initial events and set RMT_CHn_TX_LIM_REG to cause an RMT_CHn_TX_THR_EVENT_INT interrupt before the wraparound Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 84 • RMT_CHn_TX_THR_EVENT_INT: Triggered when the number of events the transmitter has sent matches the contents of the RMT_CHn_TX_LIM_REG register. • RMT_CHn_TX_END_INT: Triggered when the transmitter has finished transmitting the signal. • RMT_CHn_RX_END_INT: Triggered when the receiver has finished receiving a signal. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 85 Channel 4 Tx event configuration register 0x3FF560E0 RMT_CH5_TX_LIM_REG Channel 5 Tx event configuration register 0x3FF560E4 RMT_CH6_TX_LIM_REG Channel 6 Tx event configuration register 0x3FF560E8 RMT_CH7_TX_LIM_REG Channel 7 Tx event configuration register 0x3FF560EC Other registers RMT_APB_CONF_REG RMT-wide configuration register 0x3FF560F0 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 86 In receive mode, when no edge is detected on the input signal for longer than reg_idle_thres_chn channel clock cycles, the receive process is finished. (R/W) RMT_DIV_CNT_CHn This register is used to set the divider for the channel clock of channel n. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 87 Set this bit to reset write ram address for channel by receiver access. (R/W) RMT_RX_EN_CHn Set this bit to enable receiving data on channel n. (R/W) RMT_TX_START_CHn Set this bit to start sending data on channel n. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 88 RMT_CHn_ERR_INT_ST The masked interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO) RMT_CHn_RX_END_INT_ST The masked interrupt status bit for the RMT_CHn_RX_END_INT inter- rupt. (RO) RMT_CHn_TX_END_INT_ST The masked interrupt status bit for the RMT_CHn_TX_END_INT inter- rupt. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 89 RMT_CHn_TX_THR_EVENT_INT terrupt. (WO) RMT_CHn_ERR_INT_CLR Set this bit to clear the RMT_CHn_ERRINT interrupt. (WO) RMT_CHn_RX_END_INT_CLR Set this bit to clear the RMT_CHn_RX_END_INT interrupt. (WO) RMT_CHn_TX_END_INT_CLR Set this bit to clear the RMT_CHn_TX_END_INT interrupt. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 90 0x00000000 Reset RMT_MEM_TX_WRAP_EN bit enables wraparound mode: when the transmitter of a channel has reached the end of its memory block, it will resume sending at the start of its memory region. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 91 LCTR_MODE and HCTR_MODE modify this behaviour as such when the control input has the corresponding low Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 92 This is most useful when PCNT_THR_L_LIM_Un is set to a negative number. • Two threshold values: Triggered when PULSE_CNT = PCNT_THR_THRES0_Un PCNT_THR_THRES1_Un. • Zero: Triggered when PULSE_CNT = 0. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 93 7.2.5 Interrupts PCNT_CNT_THR_EVENT_Un_INT: This interrupt gets triggered when one of the five channel comparators detects a match. 7.3 Register Summary Name Description Address Access Configuration registers PCNT_U0_CONF0_REG Configuration register 0 for unit 0 0x3FF57000 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 94 Counter value for unit 7 0x3FF5707C Control registers PCNT_CTRL_REG Control register for all counters 0x3FF570B0 Interrupt registers PCNT_INT_RAW_REG Raw interrupt status 0x3FF57080 PCNT_INT_ST_REG Masked interrupt status 0x3FF57084 PCNT_INT_ENA_REG Interrupt enable bits 0x3FF57088 PCNT_INT_CLR_REG Interrupt clear bits 0x3FF5708C Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 95 This is the enable bit for unit n’s input filter. (R/W) PCNT_FILTER_THRES_Un This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses lasting shorter than this will be ignored when the filter is enabled. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 96 This register is used to configure the thr_h_lim value for unit n. (R/W) Register 7.4: PCNT_Un_CNT_REG (n: 0-7) (0x28+0x0C*n) 0x00000 Reset PCNT_PLUS_CNT_Un This register stores the current pulse count value for unit n. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 97 PCNT_CNT_THR_EVENT_Un_INT_RAW The interrupt status PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Register 7.6: PCNT_INT_ST_REG (0x0084) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_ST The masked interrupt status PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Register 7.7: PCNT_INT_ENA_REG (0x0088) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_ENA The interrupt enable PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 98 PCNT_CNT_THR_EVENT_Un_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_Un_INT interrupt. (WO) Register 7.9: PCNT_CTRL_REG (0x00b0) 0x0000 Reset PCNT_CNT_PAUSE_Un Set this bit to freeze unit n’s counter. (R/W) PCNT_PLUS_CNT_RST_Un Set this bit to clear unit n’s counter. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 99 There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-reload-capable up/downcounters. The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated by in TIMGn_Tx; the blocks themselves are indicated by an n.
  • Page 100 0x3FF5F010 0x3FF60010 R/W TIMGn_T0ALARMHI_REG Timer 0 alarm value, high bits 0x3FF5F014 0x3FF60014 R/W TIMGn_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x3FF5F018 0x3FF60018 R/W Write reload timer from TIMGn_T0LOAD_REG 0x3FF5F020 0x3FF60020 WO TIMGn_T0_(LOADLOLOADHI)_REG Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 101 0x3FF5F064 0x3FF60064 R/W Interrupt registers TIMGn_Tx_INT_RAW_REG Raw interrupt status 0x3FF5F09C 0x3FF6009C RO TIMGn_Tx_INT_ST_REG Masked interrupt status 0x3FF5F0A0 0x3FF600A0 RO TIMGn_Tx_INT_ENA_REG Interrupt enable bits 0x3FF5F098 0x3FF60098 R/W TIMGn_Tx_INT_CLR_REG Interrupt clear bits 0x3FF5F0A4 0x3FF600A4 WO Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 102 (RO) Register 8.3: TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x) 0x000000000 Reset TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter of timer can be read here. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 103 TIMGn_TxLOADLO_REG Low 32 bits of the value that a reload will load into timer time-base counter. (R/W) Register 8.8: TIMGn_TxLOADHI_REG (x: 0-1) (0x1C+0x24*x) 0x000000000 Reset TIMGn_TxLOADHI_REG High 32 bits of the value that a reload will load into timer time-base counter. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 104 TIMGn_Tx_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W) TIMGn_Tx_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 105 TIMGn_Tx_WDTCONFIG3_REG Stage 1 timeout value, in MWDT clock cycles. (R/W) Register 8.14: TIMGn_Tx_WDTCONFIG4_REG (0x0058) 0x0000FFFFF Reset TIMGn_Tx_WDTCONFIG4_REG Stage 2 timeout value, in MWDT clock cycles. (R/W) Register 8.15: TIMGn_Tx_WDTCONFIG5_REG (0x005c) 0x0000FFFFF Reset TIMGn_Tx_WDTCONFIG5_REG Stage 3 timeout value, in MWDT clock cycles. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 106 TIMGn_Tx_INT_WDT_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_WDT_INT interrupt. (R/W) (R/W) TIMGn_Tx_INT_T1_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T1_INT interrupt. (R/W) (R/W) TIMGn_Tx_INT_T0_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T0_INT interrupt. (R/W) (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 107 TIMGn_Tx_INT_WDT_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_WDT_INT terrupt. (RO) TIMGn_Tx_INT_T1_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T1_INT interrupt. (RO) TIMGn_Tx_INT_T0_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T0_INT interrupt. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 108 Register 8.21: TIMGn_Tx_INT_CLR_REG (0x00a4) Reset TIMGn_Tx_INT_WDT_INT_CLR Set this bit to clear the TIMGn_Tx_INT_WDT_INT interrupt. (WO) TIMGn_Tx_INT_T1_INT_CLR Set this bit to clear the TIMGn_Tx_INT_T1_INT interrupt. (WO) TIMGn_Tx_INT_T0_INT_CLR Set this bit to clear the TIMGn_Tx_INT_T0_INT interrupt. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 109 9. Watchdog Timers 9.1 Introduction The ESP32 has three watchdog timers: one in each of the two timer modules (called Main System Watchdog Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These watchdog timers are intended to recover from an unforeseen fault, causing the application program to abandon its normal sequence.
  • Page 110 RTC when it expires. After booting, the register TIMERS_WDT_FLASHBOOT_MOD_EN should be cleared to stop the flash boot protection procedure for the MWDT, and RTC_CNTL_WDT_FLASHBOOT_MOD_EN should be cleared to do the same for the RWDT. After this, the MWDT and RWDT can be configured by software. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 111 The MWDT registers are part of the timer submodule and are described in the Timer Registers section. The RWDT registers are part of the RTC submodule and are described in the RTC Registers section. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 112: Operation Mode

    AES Accelerator will store back the resulting ciphertext in the AES_TEXT_m_REG registers. To enable AES-128/192/256 decryption, initialize the AES_TEXT_m_REG registers with ciphertext before decryption. When decryption is finished, the AES Accelerator will store back the resulting plaintext in the AES_TEXT_m_REG registers. Espressif Systems ESP32 Technical Reference Manual V1.0...

  • Page 113: Key Endianness

    AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] State AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 114 Table 28: AES-128 Key Endianness AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] w[0] w[1] w[2] w[3] [31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [31:24] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [23:16] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [15:8] AES_KEY_3_REG[23:16]...
  • Page 115 Encrypted/decrypted data registers AES_TEXT_0_REG AES encrypted/decrypted data register 0 0x3FF01030 AES_TEXT_1_REG AES encrypted/decrypted data register 1 0x3FF01034 AES_TEXT_2_REG AES encrypted/decrypted data register 2 0x3FF01038 AES_TEXT_3_REG AES encrypted/decrypted data register 3 0x3FF0103C Control/status registers Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 116 10.4 Register summary 10 AES ACCELERATOR Name Description Address Access AES_START_REG AES operation start control register 0x3FF01000 AES_IDLE_REG AES idle status register 0x3FF01004 Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 117 (R/W) Register 10.4: AES_KEY_n_REG (n: 0-7) (0x10+4*n) 0x000000000 Reset AES_KEY_n_REG (n: 0-7) AES key material register. (R/W) Register 10.5: AES_TEXT_m_REG (m: 0-3) (0x30+4*m) 0x000000000 Reset AES_TEXT_m_REG (m: 0-3) Plaintext and ciphertext register. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 118 10.5 Registers 10 AES ACCELERATOR Register 10.6: AES_ENDIAN_REG (0x040) 0x0000000 Reset AES_ENDIAN Endianness selection register. See Table for details. (R/W) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 119 H in the message (N ) digest is stored in SHA_TEXT_0_REG. In the same fashion, the second left-most word H in the message digest is stored in SHA_TEXT_1_REG, etc. Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 120 SHA encrypted/decrypted data register 3 0x3FF0300C SHA_TEXT_4_REG SHA encrypted/decrypted data register 4 0x3FF03010 SHA_TEXT_5_REG SHA encrypted/decrypted data register 5 0x3FF03014 SHA_TEXT_6_REG SHA encrypted/decrypted data register 6 0x3FF03018 SHA_TEXT_7_REG SHA encrypted/decrypted data register 7 0x3FF0301C Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 121 SHA_SHA512_START_REG Control register to initiate SHA512 operation 0x3FF030B0 SHA_SHA512_CONTINUE_REG Control register to continue SHA512 operation 0x3FF030B4 Control register to calculate the final SHA512 SHA_SHA512_LOAD_REG 0x3FF030B8 hash SHA_SHA512_BUSY_REG Status register for SHA512 operation 0x3FF030BC Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 122 SHA_SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. (WO) Register 11.4: SHA_SHA1_LOAD_REG (0x088) 0x00000000 Reset SHA_SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final the message hash. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 123 SHA_SHA256_CONTINUE Write 1 to continue the SHA-256 operation with subsequent blocks. (WO) Register 11.8: SHA_SHA256_LOAD_REG (0x098) 0x00000000 Reset SHA_SHA256_LOAD Write 1 to finish the SHA-256 operation to calculate the final the message hash. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 124 SHA_SHA384_CONTINUE Write 1 to continue the SHA-384 operation with subsequent blocks. (WO) Register 11.12: SHA_SHA384_LOAD_REG (0x0A8) 0x00000000 Reset SHA_SHA384_LOAD Write 1 to finish the SHA-384 operation to calculate the final the message hash. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 125 SHA_SHA512_CONTINUE Write 1 to continue the SHA-512 operation with subsequent blocks. (WO) Register 11.16: SHA_SHA512_LOAD_REG (0x0B8) 0x00000000 Reset SHA_SHA512_LOAD Write 1 to finish the SHA-512 operation to calculate the final the message hash. (WO) Espressif Systems ESP32 Technical Reference Manual V1.0...
  • Page 126 11.5 Registers 11 SHA ACCELERATOR Register 11.17: SHA_SHA512_BUSY_REG (0x0BC) 0x00000000 Reset SHA_SHA512_BUSY SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if idle. (RO) Espressif Systems ESP32 Technical Reference Manual V1.0...

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