Key Endianness - Espressif Systems ESP32 Technical Reference Manual

10.3 Functional Description
10.3.3 Endianness

Key Endianness

Bit 0 and bit 1 in AES_ENDIAN_REG define the key endianness. For detailed information, please refer to Table
28, Table 29 and Table 30. w[0]
Nk words of the expanded key" as specified in "5.2: Key Expansion" of FIPS PUB 197. "Column Bit" specifies
the bytes in the word from w[0] to w[7]. The bytes of AES_KEY_n_REG comprise "the first Nk words of the
expanded key".
Text Endianness
Bit 2 and bit 3 in AES_ENDIAN_REG define the endianness of input text, while Bit 4 and Bit 5 define the
endianness of output text. The input text refers to the plaintext in AES-128/192/256 encryption and the
ciphertext in decryption. The output text refers to the ciphertext in AES-128/192/256 encryption and the plaintext
in decryption. For details, please refer to Table 27. "State" in Table
FIPS PUB 197: "The AES algorithm operations are performed on a two-dimensional array of bytes called the
State". The ciphertext or plaintexts stored in each byte of AES_KEY_n_REG comprise the State.
AES_ENDIAN_REG[3]/[5] AES_ENDIAN_REG[2]/[4]
0 0
0 0
0 0
0 0
Espressif Systems
~ w[3] in Table 28, w[0] ~
Table 27: AES Text Endianness
State
0
0 AES_KEY_3_REG[31:24]
1 AES_KEY_3_REG[23:16]
r
2 AES_KEY_3_REG[15:8]
3 AES_KEY_3_REG[7:0]
State
0
0 AES_KEY_3_REG[7:0]
1 AES_KEY_3_REG[15:8]
r
2 AES_KEY_3_REG[23:16]
3 AES_KEY_3_REG[31:24]
State
0
0 AES_KEY_3_REG[31:24]
1 AES_KEY_3_REG[23:16]
r
2 AES_KEY_3_REG[15:8]
3 AES_KEY_3_REG[7:0]
State
0
0 AES_KEY_3_REG[7:0]
1 AES_KEY_3_REG[15:8]
r
2 AES_KEY_3_REG[23:16]
3 AES_KEY_3_REG[31:24]
112
w[5] in Table 29 and w[0]
27 is defined as that in "3.4: The State" of
Plaintext/clphertext
c
1 2
AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24]
AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16]
AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8]
AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0]
c
1 2
AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0]
AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8]
AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16]
AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24]
c
1 2
AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24]
AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16]
AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8]
AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0]
c
1 2
AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0]
AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8]
AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16]
AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24]
ESP32 Technical Reference Manual V1.0
10 AES ACCELERATOR
~ w[7] in Table 30 are "the first
3
AES_KEY_0_REG[31:24]
AES_KEY_0_REG[23:16]
AES_KEY_0_REG[15:8]
AES_KEY_0_REG[7:0]
3
AES_KEY_0_REG[7:0]
AES_KEY_0_REG[15:8]
AES_KEY_0_REG[23:16]
AES_KEY_0_REG[31:24]
3
AES_KEY_0_REG[31:24]
AES_KEY_0_REG[23:16]
AES_KEY_0_REG[15:8]
AES_KEY_0_REG[7:0]
3
AES_KEY_0_REG[7:0]
AES_KEY_0_REG[15:8]
AES_KEY_0_REG[23:16]
AES_KEY_0_REG[31:24]