Espressif Systems ESP32 Technical Reference Manual page 20

PRO_CPU
Peripheral Interrupt
Status Register
Configuration Register
Bit Name
PRO_SPI2_DMA_INT_MAP_REG 21
PRO_SPI3_DMA_INT_MAP_REG 22
PRO_WDG_INT_MAP_REG 23
PRO_TIMER_INT1_MAP_REG 24
PRO_TIMER_INT2_MAP_REG 25
PRO_TG_T0_EDGE_INT_MAP_REG 26 PRO_INTR_STATUS_REG_1
PRO_TG_T1_EDGE_INT_MAP_REG 27
PRO_TG_WDT_EDGE_INT_MAP_REG 28
PRO_TG_LACT_EDGE_INT_MAP_REG 29
PRO_TG1_T0_EDGE_INT_MAP_REG 30
PRO_TG1_T1_EDGE_INT_MAP_REG 31
PRO_TG1_WDT_EDGE_INT_MAP_REG 0
PRO_TG1_LACT_EDGE_INT_MAP_REG 1
PRO_MMU_IA_INT_MAP_REG 2 PRO_INTR_STATUS_REG_2
PRO_MPU_IA_INT_MAP_REG 3
PRO_CACHE_IA_INT_MAP_REG 4
Peripheral Interrupt Source
No. Name
53 SPI2_DMA_INT
54 SPI3_DMA_INT
55 WDG_INT
56 TIMER_INT1
57 TIMER_INT2
58 TG_T0_EDGE_INT
59 TG_T1_EDGE_INT
60 TG_WDT_EDGE_INT
61 TG_LACT_EDGE_INT
62 TG1_T0_EDGE_INT
63 TG1_T1_EDGE_INT
64 TG1_WDT_EDGE_INT
65 TG1_LACT_EDGE_INT
66 MMU_IA_INT
67 MPU_IA_INT
68 CACHE_IA_INT
APP_CPU
Peripheral Interrupt
Status Register
No. Configuration Register
Name Bit
53 21 APP_SPI2_DMA_INT_MAP_REG
54 22 APP_SPI3_DMA_INT_MAP_REG
55 23 APP_WDG_INT_MAP_REG
56 24 APP_TIMER_INT1_MAP_REG
57 25 APP_TIMER_INT2_MAP_REG
58 APP_INTR_STATUS_REG_1 26 APP_TG_T0_EDGE_INT_MAP_REG
59 27 APP_TG_T1_EDGE_INT_MAP_REG
60 28 APP_TG_WDT_EDGE_INT_MAP_REG
61 29 APP_TG_LACT_EDGE_INT_MAP_REG
62 30 APP_TG1_T0_EDGE_INT_MAP_REG
63 31 APP_TG1_T1_EDGE_INT_MAP_REG
64 0 APP_TG1_WDT_EDGE_INT_MAP_REG
65 1 APP_TG1_LACT_EDGE_INT_MAP_REG
66 APP_INTR_STATUS_REG_2 2 APP_MMU_IA_INT_MAP_REG
67 3 APP_MPU_IA_INT_MAP_REG
68 4 APP_CACHE_IA_INT_MAP_REG