Espressif Systems ESP32 Technical Reference Manual page 87

6.4 Registers
31
0x0000
RMT_IDLE_OUT_EN_CHn
RMT_IDLE_OUT_LV_CHn
(R/W)
RMT_REF_ALWAYS_ON_CHn
0:clk_ref. (R/W)
RMT_REF_CNT_RST_CHn
RMT_RX_FILTER_THRES_CHn
is smaller than this value, in APB clock periods. (R/W)
RMT_RX_FILTER_EN_CHn
RMT_TX_CONTI_MODE_CHn
the transmitter will restart transmission. This results in a repeating output signal. (R/W)
RMT_MEM_OWNER_CHn
RAM; 0: transmitter uses the RAM. (R/W)
RMT_MEM_RD_RST_CHn
(R/W)
RMT_MEM_WR_RST_CHn
(R/W)
RMT_RX_EN_CHn
RMT_TX_START_CHn
Espressif Systems
Register 6.2: RMT_CHnCONF1_REG (n: 0-7) (0x005c+8*n)
20 19 18 17
0 0 0
This is the output enable control bit for channel
This bit configures the output signals level for channel
This bit is used to select the channels base clock.
Setting this bit resets the clock divider of channel n. (R/W)
In receive mode, channel
This is the receive filter enable bit for channel n. (R/W)
If this bit is set, instead of going to idle when the transmission ends,
This bit marks channel n's RAM block ownership. 1: receiver uses the
Set this bit to reset read ram address for channel
Set this bit to reset write ram address for channel
Set this bit to enable receiving data on channel n. (R/W)
Set this bit to start sending data on channel n. (R/W)
6 REMOTE CONTROLLER PERIPHERAL
16 15
0 0x00F
n ignores input pulse when the pulse width
86 ESP32 Technical Reference Manual V1.0
8 7 6 5 4 3 2 1
0 0 1 0 0 0 0
n in IDLE state. (R/W)
n in IDLE state.
1:clk_apb;
n by transmitter access.
n by receiver access.
0
0 Reset